CLKMGR Simulation Results

Wednesday August 14 2024 23:02:33 UTC

GitHub Revision: 584c3d46af

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 75916000169703078066460267353397937307391759551032957123310220571514951708138

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 0 50 0.00
V1 csr_hw_reset clkmgr_csr_hw_reset 1.000s 22.587us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 1.030s 97.995us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 11.020s 1.908ms 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 1.670s 59.942us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 1.860s 39.485us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 1.030s 97.995us 20 20 100.00
clkmgr_csr_aliasing 1.670s 59.942us 5 5 100.00
V1 TOTAL 55 105 52.38
V2 peri_enables clkmgr_peri 0 50 0.00
V2 trans_enables clkmgr_trans 0 50 0.00
V2 extclk clkmgr_extclk 0 50 0.00
V2 clk_status clkmgr_clk_status 0 50 0.00
V2 jitter clkmgr_smoke 0 50 0.00
V2 frequency clkmgr_frequency 0 50 0.00
V2 frequency_timeout clkmgr_frequency_timeout 0 50 0.00
V2 frequency_overflow clkmgr_frequency 0 50 0.00
V2 stress_all clkmgr_stress_all 0 50 0.00
V2 intr_test clkmgr_intr_test 0.950s 119.990us 50 50 100.00
V2 alert_test clkmgr_alert_test 0 50 0.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 3.480s 243.149us 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 3.480s 243.149us 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 1.000s 22.587us 5 5 100.00
clkmgr_csr_rw 1.030s 97.995us 20 20 100.00
clkmgr_csr_aliasing 1.670s 59.942us 5 5 100.00
clkmgr_same_csr_outstanding 1.660s 152.265us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 1.000s 22.587us 5 5 100.00
clkmgr_csr_rw 1.030s 97.995us 20 20 100.00
clkmgr_csr_aliasing 1.670s 59.942us 5 5 100.00
clkmgr_same_csr_outstanding 1.660s 152.265us 20 20 100.00
V2 TOTAL 90 490 18.37
V2S tl_intg_err clkmgr_sec_cm 0 5 0.00
clkmgr_tl_intg_err 4.590s 914.468us 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 2.980s 495.127us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 2.980s 495.127us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 2.980s 495.127us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 2.980s 495.127us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 4.730s 931.327us 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 4.590s 914.468us 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 0 50 0.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 0 50 0.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 2.980s 495.127us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 0 50 0.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 0 50 0.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 0 50 0.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 0 50 0.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 0 50 0.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 1.030s 97.995us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 0 5 0.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 1.030s 97.995us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 1.030s 97.995us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 0 5 0.00
V2S TOTAL 60 315 19.05
V3 regwen clkmgr_regwen 0 50 0.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 0 50 0.00
V3 TOTAL 0 100 0.00
TOTAL 205 1010 20.30

Testplan Progress

Items Total Written Passing Progress
V1 6 6 5 83.33
V2 11 11 3 27.27
V2S 9 9 3 33.33
V3 2 2 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
54.76 41.92 57.65 81.32 0.00 48.71 89.43 64.27

Failure Buckets

Past Results