CLKMGR Simulation Results

Thursday August 15 2024 23:02:21 UTC

GitHub Revision: d09e282b26

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 47908880312501934977153450267828796412449789719488445881682136509150457490963

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.570s 267.373us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 1.090s 123.923us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 1.010s 129.543us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 11.840s 1.891ms 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 1.900s 110.138us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 2.210s 112.016us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 1.010s 129.543us 20 20 100.00
clkmgr_csr_aliasing 1.900s 110.138us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 0.880s 69.826us 50 50 100.00
V2 trans_enables clkmgr_trans 1.440s 202.081us 50 50 100.00
V2 extclk clkmgr_extclk 1.630s 289.859us 50 50 100.00
V2 clk_status clkmgr_clk_status 1.050s 164.755us 50 50 100.00
V2 jitter clkmgr_smoke 1.570s 267.373us 50 50 100.00
V2 frequency clkmgr_frequency 17.810s 2.239ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 17.450s 2.417ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 17.810s 2.239ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.490m 12.090ms 50 50 100.00
V2 intr_test clkmgr_intr_test 0.790s 72.251us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.380s 239.542us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 3.780s 223.126us 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 3.780s 223.126us 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 1.090s 123.923us 5 5 100.00
clkmgr_csr_rw 1.010s 129.543us 20 20 100.00
clkmgr_csr_aliasing 1.900s 110.138us 5 5 100.00
clkmgr_same_csr_outstanding 2.910s 676.059us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 1.090s 123.923us 5 5 100.00
clkmgr_csr_rw 1.010s 129.543us 20 20 100.00
clkmgr_csr_aliasing 1.900s 110.138us 5 5 100.00
clkmgr_same_csr_outstanding 2.910s 676.059us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 5.730s 1.497ms 5 5 100.00
clkmgr_tl_intg_err 4.640s 1.027ms 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 3.180s 696.051us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 3.180s 696.051us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 3.180s 696.051us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 3.180s 696.051us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 5.380s 1.185ms 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 4.640s 1.027ms 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 17.810s 2.239ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 17.450s 2.417ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 3.180s 696.051us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 2.630s 627.655us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.130s 115.365us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.730s 334.225us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.100s 86.758us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.480s 239.315us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 1.010s 129.543us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 5.730s 1.497ms 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 1.010s 129.543us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 1.010s 129.543us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 5.730s 1.497ms 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 7.160s 1.249ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 2.517m 22.184ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.51 99.15 95.76 100.00 100.00 98.81 97.02 98.80

Past Results