CLKMGR Simulation Results

Friday August 16 2024 23:02:10 UTC

GitHub Revision: 76588857da

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107397868712693014844033025164446565408841343499325418676943424680076749785789

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.160s 127.550us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 0.950s 58.232us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 0.920s 49.034us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 10.620s 1.321ms 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 3.200s 666.335us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 1.870s 60.433us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 0.920s 49.034us 20 20 100.00
clkmgr_csr_aliasing 3.200s 666.335us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 0.940s 98.093us 50 50 100.00
V2 trans_enables clkmgr_trans 1.590s 238.674us 50 50 100.00
V2 extclk clkmgr_extclk 1.390s 166.528us 50 50 100.00
V2 clk_status clkmgr_clk_status 0.920s 105.143us 50 50 100.00
V2 jitter clkmgr_smoke 1.160s 127.550us 50 50 100.00
V2 frequency clkmgr_frequency 19.140s 2.362ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 17.270s 2.299ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 19.140s 2.362ms 50 50 100.00
V2 stress_all clkmgr_stress_all 2.041m 16.544ms 50 50 100.00
V2 intr_test clkmgr_intr_test 0.830s 84.778us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.530s 261.684us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 5.000s 1.196ms 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 5.000s 1.196ms 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 0.950s 58.232us 5 5 100.00
clkmgr_csr_rw 0.920s 49.034us 20 20 100.00
clkmgr_csr_aliasing 3.200s 666.335us 5 5 100.00
clkmgr_same_csr_outstanding 1.850s 189.798us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 0.950s 58.232us 5 5 100.00
clkmgr_csr_rw 0.920s 49.034us 20 20 100.00
clkmgr_csr_aliasing 3.200s 666.335us 5 5 100.00
clkmgr_same_csr_outstanding 1.850s 189.798us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 4.390s 815.911us 5 5 100.00
clkmgr_tl_intg_err 4.140s 608.214us 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 2.810s 431.240us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 2.810s 431.240us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 2.810s 431.240us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 2.810s 431.240us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 3.630s 292.322us 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 4.140s 608.214us 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 19.140s 2.362ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 17.270s 2.299ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 2.810s 431.240us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 1.700s 321.547us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.420s 213.343us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.300s 169.324us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.300s 176.020us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.330s 177.623us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 0.920s 49.034us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 4.390s 815.911us 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 0.920s 49.034us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 0.920s 49.034us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 4.390s 815.911us 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 6.980s 1.315ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 3.123m 49.541ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.51 99.15 95.80 100.00 100.00 98.81 97.02 98.80

Past Results