CLKMGR Simulation Results

Saturday August 17 2024 23:02:17 UTC

GitHub Revision: 76588857da

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 94235727392619910305578226901221990521512464990339520078429467885466612377995

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.120s 116.565us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 0.910s 90.198us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 1.010s 55.121us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 10.670s 1.656ms 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 1.790s 56.672us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 2.420s 525.961us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 1.010s 55.121us 20 20 100.00
clkmgr_csr_aliasing 1.790s 56.672us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 1.130s 164.922us 50 50 100.00
V2 trans_enables clkmgr_trans 1.800s 323.566us 50 50 100.00
V2 extclk clkmgr_extclk 1.310s 140.395us 50 50 100.00
V2 clk_status clkmgr_clk_status 1.040s 153.145us 50 50 100.00
V2 jitter clkmgr_smoke 1.120s 116.565us 50 50 100.00
V2 frequency clkmgr_frequency 18.400s 2.362ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 18.120s 2.420ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 18.400s 2.362ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.968m 16.142ms 50 50 100.00
V2 intr_test clkmgr_intr_test 1.030s 87.339us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.200s 182.703us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 5.950s 1.441ms 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 5.950s 1.441ms 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 0.910s 90.198us 5 5 100.00
clkmgr_csr_rw 1.010s 55.121us 20 20 100.00
clkmgr_csr_aliasing 1.790s 56.672us 5 5 100.00
clkmgr_same_csr_outstanding 2.120s 282.963us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 0.910s 90.198us 5 5 100.00
clkmgr_csr_rw 1.010s 55.121us 20 20 100.00
clkmgr_csr_aliasing 1.790s 56.672us 5 5 100.00
clkmgr_same_csr_outstanding 2.120s 282.963us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 5.030s 935.297us 5 5 100.00
clkmgr_tl_intg_err 3.410s 383.111us 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 2.870s 773.160us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 2.870s 773.160us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 2.870s 773.160us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 2.870s 773.160us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 4.310s 767.858us 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 3.410s 383.111us 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 18.400s 2.362ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 18.120s 2.420ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 2.870s 773.160us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 2.310s 497.711us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.790s 326.867us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.060s 110.050us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.410s 207.347us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.800s 356.414us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 1.010s 55.121us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 5.030s 935.297us 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 1.010s 55.121us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 1.010s 55.121us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 5.030s 935.297us 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 6.590s 1.978ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 3.170m 47.112ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.02 98.80

Past Results