CLKMGR Simulation Results

Sunday August 18 2024 23:02:23 UTC

GitHub Revision: f1535c5540

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29514139809134543525249635699831421949407409612590789671953066019961489233719

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.360s	193.560us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	1.000s	120.856us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	1.080s	151.736us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	12.840s	2.804ms	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	1.590s	96.874us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	1.930s	341.578us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	1.080s	151.736us	20	20	100.00
		clkmgr_csr_aliasing	1.590s	96.874us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	1.150s	146.342us	50	50	100.00
V2	trans_enables	clkmgr_trans	2.560s	484.860us	50	50	100.00
V2	extclk	clkmgr_extclk	1.270s	124.398us	50	50	100.00
V2	clk_status	clkmgr_clk_status	1.110s	102.885us	50	50	100.00
V2	jitter	clkmgr_smoke	1.360s	193.560us	50	50	100.00
V2	frequency	clkmgr_frequency	19.090s	2.364ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	18.080s	2.422ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	19.090s	2.364ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	1.494m	11.948ms	50	50	100.00
V2	intr_test	clkmgr_intr_test	0.860s	105.871us	50	50	100.00
V2	alert_test	clkmgr_alert_test	1.060s	96.211us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	7.260s	1.749ms	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	7.260s	1.749ms	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	1.000s	120.856us	5	5	100.00
		clkmgr_csr_rw	1.080s	151.736us	20	20	100.00
		clkmgr_csr_aliasing	1.590s	96.874us	5	5	100.00
		clkmgr_same_csr_outstanding	3.340s	931.942us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	1.000s	120.856us	5	5	100.00
		clkmgr_csr_rw	1.080s	151.736us	20	20	100.00
		clkmgr_csr_aliasing	1.590s	96.874us	5	5	100.00
		clkmgr_same_csr_outstanding	3.340s	931.942us	20	20	100.00
V2		TOTAL			490	490	100.00
V2S	tl_intg_err	clkmgr_sec_cm	3.470s	347.807us	5	5	100.00
		clkmgr_tl_intg_err	5.610s	1.434ms	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	2.500s	451.620us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	2.500s	451.620us	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	2.500s	451.620us	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	2.500s	451.620us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	6.330s	1.650ms	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	5.610s	1.434ms	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	19.090s	2.364ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	18.080s	2.422ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	2.500s	451.620us	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	1.680s	298.098us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	1.610s	301.156us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	1.350s	196.051us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	1.590s	292.439us	50	50	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	1.540s	238.806us	50	50	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	1.080s	151.736us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	3.470s	347.807us	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	1.080s	151.736us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	1.080s	151.736us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	3.470s	347.807us	5	5	100.00
V2S		TOTAL			315	315	100.00
V3	regwen	clkmgr_regwen	7.560s	2.281ms	50	50	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	2.592m	42.541ms	48	50	96.00
V3		TOTAL			98	100	98.00
		TOTAL			1008	1010	99.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.52	99.15	95.88	100.00	100.00	98.81	97.02	98.80

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:771) [clkmgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test clkmgr_stress_all_with_rand_reset has 1 failures.

    • 14.clkmgr_stress_all_with_rand_reset.66031149855613905189549075217974234659439164464213276714980989039970023960467
      Line 396, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/14.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1947094538 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 1947094538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(lc_clk_byp_req || (io_clk_byp_req_o != MuBi4False))' has 1 failures:

  • Test clkmgr_stress_all_with_rand_reset has 1 failures.

    • 46.clkmgr_stress_all_with_rand_reset.47478064769190575113128835402640900472751789131144182588466632178442733505615
      Line 344, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/46.clkmgr_stress_all_with_rand_reset/latest/run.log

            Offending '(lc_clk_byp_req || (io_clk_byp_req_o != MuBi4False))'
        UVM_ERROR @ 2237613344 ps: (clkmgr_extclk_sva_if.sv:41) [ASSERT FAILED] IoClkBypReqFall_A
        UVM_INFO @ 2237613344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• dv
• 2024.08.18_08.52.55
• 2024.08.17_07.35.08
• 2024.08.16_08.51.33
• 2024.08.15_05.50.45
• 2024.08.14_08.55.02