CLKMGR Simulation Results

Monday August 19 2024 23:02:17 UTC

GitHub Revision: e45ccd274a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 28901767565311589526059483176077826609560752276120463932311122284088110669824

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.580s 276.922us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 0.930s 54.208us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 1.150s 139.339us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 13.270s 2.572ms 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 1.400s 26.060us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 2.150s 118.227us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 1.150s 139.339us 20 20 100.00
clkmgr_csr_aliasing 1.400s 26.060us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 1.110s 130.721us 50 50 100.00
V2 trans_enables clkmgr_trans 1.560s 250.488us 50 50 100.00
V2 extclk clkmgr_extclk 1.170s 100.793us 50 50 100.00
V2 clk_status clkmgr_clk_status 1.160s 194.543us 50 50 100.00
V2 jitter clkmgr_smoke 1.580s 276.922us 50 50 100.00
V2 frequency clkmgr_frequency 18.330s 2.360ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 17.320s 2.415ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 18.330s 2.360ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.616m 18.662ms 50 50 100.00
V2 intr_test clkmgr_intr_test 1.120s 166.601us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.440s 225.925us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 5.170s 932.037us 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 5.170s 932.037us 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 0.930s 54.208us 5 5 100.00
clkmgr_csr_rw 1.150s 139.339us 20 20 100.00
clkmgr_csr_aliasing 1.400s 26.060us 5 5 100.00
clkmgr_same_csr_outstanding 2.100s 373.956us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 0.930s 54.208us 5 5 100.00
clkmgr_csr_rw 1.150s 139.339us 20 20 100.00
clkmgr_csr_aliasing 1.400s 26.060us 5 5 100.00
clkmgr_same_csr_outstanding 2.100s 373.956us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 6.400s 1.408ms 5 5 100.00
clkmgr_tl_intg_err 4.250s 633.065us 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 5.350s 1.518ms 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 5.350s 1.518ms 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 5.350s 1.518ms 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 5.350s 1.518ms 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 4.360s 721.195us 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 4.250s 633.065us 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 18.330s 2.360ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 17.320s 2.415ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 5.350s 1.518ms 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 1.990s 351.550us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.280s 185.683us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.320s 178.198us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.500s 217.677us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 2.120s 433.195us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 1.150s 139.339us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 6.400s 1.408ms 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 1.150s 139.339us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 1.150s 139.339us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 6.400s 1.408ms 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 7.890s 1.305ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 4.970m 83.492ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.51 99.15 95.80 100.00 100.00 98.81 97.02 98.80

Past Results