CLKMGR Simulation Results

Wednesday August 21 2024 01:12:47 UTC

GitHub Revision: 34b8fc33e3

Branch: earlgrey_1_0_0_2024_08_20_RC0

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 77645589415139663032322841827996135987237190720163469870959218015679941996572

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 2.090s 148.018us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 1.310s 28.332us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 1.200s 15.438us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 8.770s 485.332us 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 2.380s 187.052us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 2.000s 114.526us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 1.200s 15.438us 20 20 100.00
clkmgr_csr_aliasing 2.380s 187.052us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 1.390s 51.500us 50 50 100.00
V2 trans_enables clkmgr_trans 2.370s 131.642us 50 50 100.00
V2 extclk clkmgr_extclk 2.180s 171.336us 50 50 100.00
V2 clk_status clkmgr_clk_status 1.790s 206.428us 50 50 100.00
V2 jitter clkmgr_smoke 2.090s 148.018us 50 50 100.00
V2 frequency clkmgr_frequency 22.660s 2.478ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 20.610s 2.180ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 22.660s 2.478ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.735m 12.186ms 50 50 100.00
V2 intr_test clkmgr_intr_test 1.050s 33.592us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.980s 176.362us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 4.600s 410.238us 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 4.600s 410.238us 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 1.310s 28.332us 5 5 100.00
clkmgr_csr_rw 1.200s 15.438us 20 20 100.00
clkmgr_csr_aliasing 2.380s 187.052us 5 5 100.00
clkmgr_same_csr_outstanding 2.420s 408.772us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 1.310s 28.332us 5 5 100.00
clkmgr_csr_rw 1.200s 15.438us 20 20 100.00
clkmgr_csr_aliasing 2.380s 187.052us 5 5 100.00
clkmgr_same_csr_outstanding 2.420s 408.772us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 7.050s 1.481ms 5 5 100.00
clkmgr_tl_intg_err 3.770s 462.122us 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 2.600s 490.585us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 2.600s 490.585us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 2.600s 490.585us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 2.600s 490.585us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 5.350s 1.501ms 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 3.770s 462.122us 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 22.660s 2.478ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 20.610s 2.180ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 2.600s 490.585us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 2.520s 577.150us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.880s 158.928us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 2.100s 164.083us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 2.770s 228.023us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.940s 174.004us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 1.200s 15.438us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 7.050s 1.481ms 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 1.200s 15.438us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 1.200s 15.438us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 7.050s 1.481ms 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 10.540s 1.533ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 2.264m 30.329ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.02 98.80

Past Results