CLKMGR Simulation Results

Thursday August 22 2024 22:02:20 UTC

GitHub Revision: 0825c81be0

Branch: os_regression_2024_08_22

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 102736032995262985039236458937944411119924968439319752111682827040046827694889

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.020s 137.799us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 0.780s 27.576us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 1.140s 222.715us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 11.800s 2.971ms 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 1.710s 73.164us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 1.410s 143.900us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 1.140s 222.715us 20 20 100.00
clkmgr_csr_aliasing 1.710s 73.164us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 1.020s 167.881us 50 50 100.00
V2 trans_enables clkmgr_trans 1.590s 354.911us 50 50 100.00
V2 extclk clkmgr_extclk 1.420s 285.151us 50 50 100.00
V2 clk_status clkmgr_clk_status 0.960s 165.265us 50 50 100.00
V2 jitter clkmgr_smoke 1.020s 137.799us 50 50 100.00
V2 frequency clkmgr_frequency 18.520s 2.476ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 15.920s 2.420ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 18.520s 2.476ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.802m 14.556ms 50 50 100.00
V2 intr_test clkmgr_intr_test 0.780s 83.742us 50 50 100.00
V2 alert_test clkmgr_alert_test 0.960s 97.236us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 3.400s 404.077us 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 3.400s 404.077us 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 0.780s 27.576us 5 5 100.00
clkmgr_csr_rw 1.140s 222.715us 20 20 100.00
clkmgr_csr_aliasing 1.710s 73.164us 5 5 100.00
clkmgr_same_csr_outstanding 1.750s 210.712us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 0.780s 27.576us 5 5 100.00
clkmgr_csr_rw 1.140s 222.715us 20 20 100.00
clkmgr_csr_aliasing 1.710s 73.164us 5 5 100.00
clkmgr_same_csr_outstanding 1.750s 210.712us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 2.720s 317.148us 5 5 100.00
clkmgr_tl_intg_err 4.240s 1.049ms 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 3.190s 785.971us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 3.190s 785.971us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 3.190s 785.971us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 3.190s 785.971us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 3.690s 500.400us 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 4.240s 1.049ms 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 18.520s 2.476ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 15.920s 2.420ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 3.190s 785.971us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 1.700s 373.039us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.260s 184.702us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.750s 396.005us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.560s 305.021us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.450s 280.946us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 1.140s 222.715us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 2.720s 317.148us 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 1.140s 222.715us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 1.140s 222.715us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 2.720s 317.148us 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 6.950s 1.383ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 2.082m 19.261ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.02 98.80

Past Results