CLKMGR Simulation Results

Saturday August 24 2024 20:58:08 UTC

GitHub Revision: e733a8ef8a

Branch: os_regression_2024_08_24

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 36240513409906943553650221581975102764006655953510936167454320581301243659163

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 2.110s 176.072us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 0.870s 72.498us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 1.200s 41.172us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 7.050s 966.580us 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 1.650s 132.030us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 2.670s 243.041us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 1.200s 41.172us 20 20 100.00
clkmgr_csr_aliasing 1.650s 132.030us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 44.518s 49 50 98.00
V2 trans_enables clkmgr_trans 51.384s 48 50 96.00
V2 extclk clkmgr_extclk 2.850s 282.751us 50 50 100.00
V2 clk_status clkmgr_clk_status 51.342s 48 50 96.00
V2 jitter clkmgr_smoke 2.110s 176.072us 50 50 100.00
V2 frequency clkmgr_frequency 58.368s 48 50 96.00
V2 frequency_timeout clkmgr_frequency_timeout 58.345s 47 50 94.00
V2 frequency_overflow clkmgr_frequency 58.368s 48 50 96.00
V2 stress_all clkmgr_stress_all 2.074m 18.398ms 50 50 100.00
V2 intr_test clkmgr_intr_test 1.000s 20.798us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.690s 82.967us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 4.790s 731.297us 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 4.790s 731.297us 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 0.870s 72.498us 5 5 100.00
clkmgr_csr_rw 1.200s 41.172us 20 20 100.00
clkmgr_csr_aliasing 1.650s 132.030us 5 5 100.00
clkmgr_same_csr_outstanding 2.550s 257.055us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 0.870s 72.498us 5 5 100.00
clkmgr_csr_rw 1.200s 41.172us 20 20 100.00
clkmgr_csr_aliasing 1.650s 132.030us 5 5 100.00
clkmgr_same_csr_outstanding 2.550s 257.055us 20 20 100.00
V2 TOTAL 480 490 97.96
V2S tl_intg_err clkmgr_sec_cm 6.080s 425.509us 5 5 100.00
clkmgr_tl_intg_err 6.860s 1.085ms 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 2.820s 620.705us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 2.820s 620.705us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 2.820s 620.705us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 2.820s 620.705us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 4.000s 535.542us 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 6.860s 1.085ms 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 58.368s 48 50 96.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 58.345s 47 50 94.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 2.820s 620.705us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 51.297s 47 50 94.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 42.910s 48 50 96.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 50.125s 48 50 96.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 50.099s 49 50 98.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 49.027s 49 50 98.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 1.200s 41.172us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 6.080s 425.509us 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 1.200s 41.172us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 1.200s 41.172us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 6.080s 425.509us 5 5 100.00
V2S TOTAL 306 315 97.14
V3 regwen clkmgr_regwen 11.940s 1.126ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 5.241m 57.514ms 49 50 98.00
V3 TOTAL 99 100 99.00
TOTAL 990 1010 98.02

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 6 54.55
V2S 9 9 4 44.44
V3 2 2 1 50.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.02 98.80

Failure Buckets

Past Results