CLKMGR Simulation Results

Monday August 26 2024 23:33:20 UTC

GitHub Revision: `4674f625b3`

Branch: os_regression_2024_08_26

Simulator: VCS

Build randomization enabled with --build-seed 27137705585251537962012108482438895412147493342955425380690984800523869492310

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.590s	158.539us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	1.290s	50.248us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	1.360s	58.680us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	10.950s	2.384ms	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	1.970s	112.532us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	1.880s	374.214us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	1.360s	58.680us	20	20	100.00
		clkmgr_csr_aliasing	1.970s	112.532us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	1.630s	190.243us	50	50	100.00
V2	trans_enables	clkmgr_trans	1.760s	339.014us	50	50	100.00
V2	extclk	clkmgr_extclk	41.567s		49	50	98.00
V2	clk_status	clkmgr_clk_status	41.804s		49	50	98.00
V2	jitter	clkmgr_smoke	1.590s	158.539us	50	50	100.00
V2	frequency	clkmgr_frequency	16.990s	2.236ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	17.460s	2.422ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	16.990s	2.236ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	1.509m	12.864ms	49	50	98.00
V2	intr_test	clkmgr_intr_test	1.230s	72.991us	50	50	100.00
V2	alert_test	clkmgr_alert_test	1.570s	112.402us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	4.630s	601.535us	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	4.630s	601.535us	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	1.290s	50.248us	5	5	100.00
		clkmgr_csr_rw	1.360s	58.680us	20	20	100.00
		clkmgr_csr_aliasing	1.970s	112.532us	5	5	100.00
		clkmgr_same_csr_outstanding	1.890s	279.218us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	1.290s	50.248us	5	5	100.00
		clkmgr_csr_rw	1.360s	58.680us	20	20	100.00
		clkmgr_csr_aliasing	1.970s	112.532us	5	5	100.00
		clkmgr_same_csr_outstanding	1.890s	279.218us	20	20	100.00
V2		TOTAL			487	490	99.39
V2S	tl_intg_err	clkmgr_sec_cm	4.030s	595.890us	5	5	100.00
		clkmgr_tl_intg_err	5.740s	1.086ms	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	4.530s	1.299ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	4.530s	1.299ms	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	4.530s	1.299ms	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	4.530s	1.299ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	4.700s	930.886us	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	5.740s	1.086ms	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	16.990s	2.236ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	17.460s	2.422ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	4.530s	1.299ms	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	41.798s		49	50	98.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	41.780s		49	50	98.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	41.770s		49	50	98.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	41.752s		49	50	98.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	41.745s		49	50	98.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	1.360s	58.680us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	4.030s	595.890us	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	1.360s	58.680us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	1.360s	58.680us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	4.030s	595.890us	5	5	100.00
V2S		TOTAL			310	315	98.41
V3	regwen	clkmgr_regwen	41.722s		49	50	98.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	5.066m	92.835ms	48	50	96.00
V3		TOTAL			97	100	97.00
		TOTAL			999	1010	98.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	8	72.73
V2S	9	9	4	44.44
V3	2	2	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.52	99.15	95.84	100.00	100.00	98.81	97.02	98.80

Failure Buckets

Job returned non-zero exit code has 10 failures:

Test clkmgr_clk_status has 1 failures.

30.clkmgr_clk_status.403214797876258909213261790571027930097207535642546443896663125806284856484
Log /workspaces/repo/scratch/os_regression_2024_08_26/clkmgr-sim-vcs/30.clkmgr_clk_status/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Aug 27 05:22 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

Test clkmgr_idle_intersig_mubi has 1 failures.

30.clkmgr_idle_intersig_mubi.100449529431082616034152150081038574629718327440138704551846777363209058977360
Log /workspaces/repo/scratch/os_regression_2024_08_26/clkmgr-sim-vcs/30.clkmgr_idle_intersig_mubi/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Aug 27 05:22 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

Test clkmgr_lc_ctrl_intersig_mubi has 1 failures.

30.clkmgr_lc_ctrl_intersig_mubi.72808215104052418599508851076342628758487525340193896654630777977436027353367
Log /workspaces/repo/scratch/os_regression_2024_08_26/clkmgr-sim-vcs/30.clkmgr_lc_ctrl_intersig_mubi/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Aug 27 05:22 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

Test clkmgr_lc_clk_byp_req_intersig_mubi has 1 failures.

30.clkmgr_lc_clk_byp_req_intersig_mubi.45795711453781751140321119383292051879131665931083947944439358238901449313099
Log /workspaces/repo/scratch/os_regression_2024_08_26/clkmgr-sim-vcs/30.clkmgr_lc_clk_byp_req_intersig_mubi/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Aug 27 05:22 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

Test clkmgr_clk_handshake_intersig_mubi has 1 failures.

30.clkmgr_clk_handshake_intersig_mubi.34146400311225972960762806529545877994237842625926328931366996950164658422777
Log /workspaces/repo/scratch/os_regression_2024_08_26/clkmgr-sim-vcs/30.clkmgr_clk_handshake_intersig_mubi/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Aug 27 05:22 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

... and 5 more tests.

UVM_ERROR (cip_base_vseq.sv:771) [clkmgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test clkmgr_stress_all_with_rand_reset has 1 failures.
  - 42.clkmgr_stress_all_with_rand_reset.35904865422708237903664594027605144625551717209056584791419656619102435215591
    Line 451, in log /workspaces/repo/scratch/os_regression_2024_08_26/clkmgr-sim-vcs/42.clkmgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10736915456 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 10736915456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```