CLKMGR Simulation Results

Wednesday August 28 2024 16:26:26 UTC

GitHub Revision: `a861deb3de`

Branch: os_regression_2024_08_28

Simulator: VCS

Build randomization enabled with --build-seed 1071354200461384473511155521960728188378582408849032283874664554749864050652

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	2.240s	191.517us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	1.210s	176.921us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	1.330s	120.417us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	8.330s	1.689ms	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	2.180s	70.083us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	2.320s	88.747us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	1.330s	120.417us	20	20	100.00
		clkmgr_csr_aliasing	2.180s	70.083us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	1.540s	104.969us	50	50	100.00
V2	trans_enables	clkmgr_trans	1.960s	272.358us	50	50	100.00
V2	extclk	clkmgr_extclk	2.080s	147.228us	50	50	100.00
V2	clk_status	clkmgr_clk_status	1.630s	148.039us	50	50	100.00
V2	jitter	clkmgr_smoke	2.240s	191.517us	50	50	100.00
V2	frequency	clkmgr_frequency	26.150s	2.475ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	22.030s	2.428ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	26.150s	2.475ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	1.443m	10.187ms	50	50	100.00
V2	intr_test	clkmgr_intr_test	1.070s	141.044us	50	50	100.00
V2	alert_test	clkmgr_alert_test	1.820s	102.075us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	8.290s	1.691ms	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	8.290s	1.691ms	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	1.210s	176.921us	5	5	100.00
		clkmgr_csr_rw	1.330s	120.417us	20	20	100.00
		clkmgr_csr_aliasing	2.180s	70.083us	5	5	100.00
		clkmgr_same_csr_outstanding	2.440s	356.177us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	1.210s	176.921us	5	5	100.00
		clkmgr_csr_rw	1.330s	120.417us	20	20	100.00
		clkmgr_csr_aliasing	2.180s	70.083us	5	5	100.00
		clkmgr_same_csr_outstanding	2.440s	356.177us	20	20	100.00
V2		TOTAL			490	490	100.00
V2S	tl_intg_err	clkmgr_sec_cm	5.110s	297.059us	5	5	100.00
		clkmgr_tl_intg_err	12.670s	3.524ms	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	2.870s	597.145us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	2.870s	597.145us	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	2.870s	597.145us	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	2.870s	597.145us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	4.170s	545.328us	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	12.670s	3.524ms	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	26.150s	2.475ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	22.030s	2.428ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	2.870s	597.145us	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	2.990s	401.956us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	2.490s	247.863us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	2.140s	176.892us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	1.446m		49	50	98.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	1.680s	100.263us	50	50	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	1.330s	120.417us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	5.110s	297.059us	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	1.330s	120.417us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	1.330s	120.417us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	5.110s	297.059us	5	5	100.00
V2S		TOTAL			314	315	99.68
V3	regwen	clkmgr_regwen	14.520s	1.307ms	50	50	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	4.003m	66.463ms	50	50	100.00
V3		TOTAL			100	100	100.00
		TOTAL			1009	1010	99.90

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	9	9	8	88.89
V3	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.51	99.15	95.80	100.00	100.00	98.81	97.02	98.80

Failure Buckets

Job returned non-zero exit code has 1 failures:

Test clkmgr_clk_handshake_intersig_mubi has 1 failures.

38.clkmgr_clk_handshake_intersig_mubi.85310078153070216792005392492190620230981707831041097821192356418994172906471
Log /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/38.clkmgr_clk_handshake_intersig_mubi/latest/run.log

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  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Aug 28 19:58 2024
  Feature removed during lmreread, or wrong
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  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255