CLKMGR Simulation Results

Sunday September 01 2024 02:56:32 UTC

GitHub Revision: `ed1c41cd0f`

Branch: os_regression_2024_08_31

Simulator: VCS

Build randomization enabled with --build-seed 79046303479535931055412478968949166876277637335647713094117953182855865639399

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	42.857s		49	50	98.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	1.480s	305.002us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	1.060s	22.664us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	6.520s	265.281us	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	1.720s	316.662us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	1.970s	330.893us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	1.060s	22.664us	20	20	100.00
		clkmgr_csr_aliasing	1.720s	316.662us	5	5	100.00
V1		TOTAL			104	105	99.05
V2	peri_enables	clkmgr_peri	1.580s	113.055us	50	50	100.00
V2	trans_enables	clkmgr_trans	2.470s	179.246us	50	50	100.00
V2	extclk	clkmgr_extclk	42.804s		49	50	98.00
V2	clk_status	clkmgr_clk_status	1.320s	50.324us	50	50	100.00
V2	jitter	clkmgr_smoke	42.857s		49	50	98.00
V2	frequency	clkmgr_frequency	42.748s		49	50	98.00
V2	frequency_timeout	clkmgr_frequency_timeout	21.580s	2.297ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	42.748s		49	50	98.00
V2	stress_all	clkmgr_stress_all	1.973m	14.114ms	50	50	100.00
V2	intr_test	clkmgr_intr_test	0.900s	49.863us	50	50	100.00
V2	alert_test	clkmgr_alert_test	42.908s		49	50	98.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	5.570s	970.178us	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	5.570s	970.178us	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	1.480s	305.002us	5	5	100.00
		clkmgr_csr_rw	1.060s	22.664us	20	20	100.00
		clkmgr_csr_aliasing	1.720s	316.662us	5	5	100.00
		clkmgr_same_csr_outstanding	1.700s	184.707us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	1.480s	305.002us	5	5	100.00
		clkmgr_csr_rw	1.060s	22.664us	20	20	100.00
		clkmgr_csr_aliasing	1.720s	316.662us	5	5	100.00
		clkmgr_same_csr_outstanding	1.700s	184.707us	20	20	100.00
V2		TOTAL			487	490	99.39
V2S	tl_intg_err	clkmgr_sec_cm	6.760s	997.300us	5	5	100.00
		clkmgr_tl_intg_err	4.290s	592.702us	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	2.490s	430.187us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	2.490s	430.187us	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	2.490s	430.187us	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	2.490s	430.187us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	3.600s	296.835us	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	4.290s	592.702us	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	42.748s		49	50	98.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	21.580s	2.297ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	2.490s	430.187us	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	2.520s	227.785us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	2.370s	174.964us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	2.390s	216.766us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	2.200s	350.756us	50	50	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	2.230s	254.885us	50	50	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	1.060s	22.664us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	6.760s	997.300us	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	1.060s	22.664us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	1.060s	22.664us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	6.760s	997.300us	5	5	100.00
V2S		TOTAL			315	315	100.00
V3	regwen	clkmgr_regwen	10.920s	953.316us	50	50	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	5.118m	73.233ms	49	50	98.00
V3		TOTAL			99	100	99.00
		TOTAL			1005	1010	99.50

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	5	83.33
V2	11	11	8	72.73
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.52	99.15	95.84	100.00	100.00	98.81	97.02	98.80

Failure Buckets

Job returned non-zero exit code has 4 failures:

Test clkmgr_alert_test has 1 failures.

31.clkmgr_alert_test.15976438602344197786881882794834448446007721495635320600422073583861556804944
Log /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/31.clkmgr_alert_test/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Sep  1 06:21 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

Test clkmgr_smoke has 1 failures.

32.clkmgr_smoke.16936024686402206053279439461669461532721016019157495704817572651480057441038
Log /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/32.clkmgr_smoke/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Sep  1 06:21 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

Test clkmgr_extclk has 1 failures.

32.clkmgr_extclk.39451684413146952721939912706151680578605787565418380218981953356276999291906
Log /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/32.clkmgr_extclk/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Sep  1 06:21 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

Test clkmgr_frequency has 1 failures.

32.clkmgr_frequency.4203220094706796268172703107409708168313910326417178280689691888681075164206
Log /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/32.clkmgr_frequency/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Sep  1 06:21 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

UVM_ERROR (cip_base_vseq.sv:771) [clkmgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test clkmgr_stress_all_with_rand_reset has 1 failures.
  - 5.clkmgr_stress_all_with_rand_reset.52427013168682959353190496831110214255167007536528904517487499895695819173673
    Line 64, in log /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/5.clkmgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  44378791 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @  44378791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```