CLKMGR Simulation Results

Tuesday September 03 2024 20:34:49 UTC

GitHub Revision: 372a6306e0

Branch: os_regression_2024_09_03

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 13282233770562214583722256565474794620746865855733889385758507057043002787586

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 2.720s 294.193us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 1.230s 35.134us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 1.470s 79.186us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 12.660s 1.989ms 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 2.660s 196.797us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 2.480s 166.480us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 1.470s 79.186us 20 20 100.00
clkmgr_csr_aliasing 2.660s 196.797us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 1.730s 138.793us 50 50 100.00
V2 trans_enables clkmgr_trans 2.610s 292.957us 50 50 100.00
V2 extclk clkmgr_extclk 2.510s 300.997us 50 50 100.00
V2 clk_status clkmgr_clk_status 2.060s 214.145us 50 50 100.00
V2 jitter clkmgr_smoke 2.720s 294.193us 50 50 100.00
V2 frequency clkmgr_frequency 26.500s 1.761ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 19.900s 2.416ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 26.500s 1.761ms 50 50 100.00
V2 stress_all clkmgr_stress_all 2.151m 13.159ms 50 50 100.00
V2 intr_test clkmgr_intr_test 1.070s 27.078us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.530s 72.638us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 6.620s 1.660ms 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 6.620s 1.660ms 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 1.230s 35.134us 5 5 100.00
clkmgr_csr_rw 1.470s 79.186us 20 20 100.00
clkmgr_csr_aliasing 2.660s 196.797us 5 5 100.00
clkmgr_same_csr_outstanding 2.910s 663.379us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 1.230s 35.134us 5 5 100.00
clkmgr_csr_rw 1.470s 79.186us 20 20 100.00
clkmgr_csr_aliasing 2.660s 196.797us 5 5 100.00
clkmgr_same_csr_outstanding 2.910s 663.379us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 6.300s 640.987us 5 5 100.00
clkmgr_tl_intg_err 5.420s 1.194ms 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 3.840s 984.184us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 3.840s 984.184us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 3.840s 984.184us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 3.840s 984.184us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 4.650s 500.707us 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 5.420s 1.194ms 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 26.500s 1.761ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 19.900s 2.416ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 3.840s 984.184us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 3.470s 449.456us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 2.070s 142.437us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 2.150s 184.536us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.820s 92.424us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 2.810s 267.096us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 1.470s 79.186us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 6.300s 640.987us 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 1.470s 79.186us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 1.470s 79.186us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 6.300s 640.987us 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 12.370s 1.169ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 2.682m 39.429ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.02 98.80

Past Results