CLKMGR Simulation Results

Monday September 09 2024 02:20:26 UTC

GitHub Revision: af2d1709f9

Branch: os_regression_2024_09_08

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 13980492992314588037778262839223440914483141513139750793389284041724730149540

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 2.750s 283.031us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 1.450s 59.805us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 1.620s 207.465us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 28.050s 7.913ms 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 2.160s 88.407us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 3.140s 402.567us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 1.620s 207.465us 20 20 100.00
clkmgr_csr_aliasing 2.160s 88.407us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 1.710s 127.679us 50 50 100.00
V2 trans_enables clkmgr_trans 2.130s 125.275us 50 50 100.00
V2 extclk clkmgr_extclk 2.280s 202.279us 50 50 100.00
V2 clk_status clkmgr_clk_status 1.530s 100.082us 50 50 100.00
V2 jitter clkmgr_smoke 2.750s 283.031us 50 50 100.00
V2 frequency clkmgr_frequency 22.320s 1.998ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 36.350s 2.296ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 22.320s 1.998ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.418m 8.908ms 50 50 100.00
V2 intr_test clkmgr_intr_test 1.420s 94.798us 50 50 100.00
V2 alert_test clkmgr_alert_test 2.290s 189.672us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 5.590s 1.376ms 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 5.590s 1.376ms 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 1.450s 59.805us 5 5 100.00
clkmgr_csr_rw 1.620s 207.465us 20 20 100.00
clkmgr_csr_aliasing 2.160s 88.407us 5 5 100.00
clkmgr_same_csr_outstanding 2.660s 266.771us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 1.450s 59.805us 5 5 100.00
clkmgr_csr_rw 1.620s 207.465us 20 20 100.00
clkmgr_csr_aliasing 2.160s 88.407us 5 5 100.00
clkmgr_same_csr_outstanding 2.660s 266.771us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 6.510s 619.085us 5 5 100.00
clkmgr_tl_intg_err 12.570s 4.226ms 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 3.780s 312.224us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 3.780s 312.224us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 3.780s 312.224us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 3.780s 312.224us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 4.960s 1.112ms 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 12.570s 4.226ms 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 22.320s 1.998ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 36.350s 2.296ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 3.780s 312.224us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 2.250s 126.512us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 2.550s 257.836us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.890s 112.726us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 2.270s 144.453us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 2.710s 256.103us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 1.620s 207.465us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 6.510s 619.085us 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 1.620s 207.465us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 1.620s 207.465us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 6.510s 619.085us 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 12.230s 1.957ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 2.950m 35.217ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.51 99.15 95.80 100.00 100.00 98.81 97.02 98.80

Past Results