CLKMGR Simulation Results

Tuesday September 10 2024 22:04:06 UTC

GitHub Revision: `25b1acbf68`

Branch: os_regression_2024_09_10

Simulator: VCS

Build randomization enabled with --build-seed 115096073277204595231937901342804627564470767004707790242822318429579153097636

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.770s	214.002us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	1.260s	35.433us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	1.630s	114.954us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	10.580s	972.410us	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	3.060s	252.448us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	2.220s	29.945us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	1.630s	114.954us	20	20	100.00
		clkmgr_csr_aliasing	3.060s	252.448us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	1.450s	109.263us	50	50	100.00
V2	trans_enables	clkmgr_trans	2.460s	536.261us	50	50	100.00
V2	extclk	clkmgr_extclk	1.910s	115.268us	50	50	100.00
V2	clk_status	clkmgr_clk_status	1.570s	158.335us	50	50	100.00
V2	jitter	clkmgr_smoke	1.770s	214.002us	50	50	100.00
V2	frequency	clkmgr_frequency	19.580s	2.235ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	17.110s	2.298ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	19.580s	2.235ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	1.803m	13.718ms	50	50	100.00
V2	intr_test	clkmgr_intr_test	1.170s	38.443us	50	50	100.00
V2	alert_test	clkmgr_alert_test	1.690s	114.811us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	6.050s	870.710us	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	6.050s	870.710us	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	1.260s	35.433us	5	5	100.00
		clkmgr_csr_rw	1.630s	114.954us	20	20	100.00
		clkmgr_csr_aliasing	3.060s	252.448us	5	5	100.00
		clkmgr_same_csr_outstanding	3.360s	680.043us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	1.260s	35.433us	5	5	100.00
		clkmgr_csr_rw	1.630s	114.954us	20	20	100.00
		clkmgr_csr_aliasing	3.060s	252.448us	5	5	100.00
		clkmgr_same_csr_outstanding	3.360s	680.043us	20	20	100.00
V2		TOTAL			490	490	100.00
V2S	tl_intg_err	clkmgr_sec_cm	5.670s	612.310us	5	5	100.00
		clkmgr_tl_intg_err	3.620s	472.027us	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	3.750s	328.227us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	3.750s	328.227us	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	3.750s	328.227us	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	3.750s	328.227us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	4.100s	248.565us	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	3.620s	472.027us	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	19.580s	2.235ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	17.110s	2.298ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	3.750s	328.227us	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	2.280s	415.262us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	2.160s	193.658us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	2.090s	188.758us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	2.020s	182.902us	50	50	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	22.153s		49	50	98.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	1.630s	114.954us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	5.670s	612.310us	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	1.630s	114.954us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	1.630s	114.954us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	5.670s	612.310us	5	5	100.00
V2S		TOTAL			314	315	99.68
V3	regwen	clkmgr_regwen	8.930s	1.407ms	50	50	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	5.398m	90.230ms	49	50	98.00
V3		TOTAL			99	100	99.00
		TOTAL			1008	1010	99.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	9	9	8	88.89
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.52	99.15	95.84	100.00	100.00	98.81	97.02	98.80

Failure Buckets

Job returned non-zero exit code has 1 failures:

Test clkmgr_div_intersig_mubi has 1 failures.

30.clkmgr_div_intersig_mubi.63253581848323468464241078152100796162629870226074242140666038305956651133132
Log /workspaces/repo/scratch/os_regression_2024_09_10/clkmgr-sim-vcs/30.clkmgr_div_intersig_mubi/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Sep 11 02:54 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

UVM_ERROR (cip_base_vseq.sv:771) [clkmgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test clkmgr_stress_all_with_rand_reset has 1 failures.
  - 31.clkmgr_stress_all_with_rand_reset.9514191767478153359548741079477622746095209332445637173874886733249045094163
    Line 216, in log /workspaces/repo/scratch/os_regression_2024_09_10/clkmgr-sim-vcs/31.clkmgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1681224367 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1681224367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```