CLKMGR Simulation Results

Wednesday September 18 2024 00:48:27 UTC

GitHub Revision: 7e34e67ade

Branch: os_regression_2024_09_17

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 4190660412037082522497784440658734031572790705268868319466386425736861254975

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 41.214s 47 50 94.00
V1 csr_hw_reset clkmgr_csr_hw_reset 1.320s 22.305us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 1.890s 180.181us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 11.930s 520.526us 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 2.990s 124.975us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 2.850s 504.070us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 1.890s 180.181us 20 20 100.00
clkmgr_csr_aliasing 2.990s 124.975us 5 5 100.00
V1 TOTAL 102 105 97.14
V2 peri_enables clkmgr_peri 42.026s 49 50 98.00
V2 trans_enables clkmgr_trans 27.961s 47 50 94.00
V2 extclk clkmgr_extclk 41.485s 47 50 94.00
V2 clk_status clkmgr_clk_status 42.491s 47 50 94.00
V2 jitter clkmgr_smoke 41.214s 47 50 94.00
V2 frequency clkmgr_frequency 27.714s 48 50 96.00
V2 frequency_timeout clkmgr_frequency_timeout 41.737s 47 50 94.00
V2 frequency_overflow clkmgr_frequency 27.714s 48 50 96.00
V2 stress_all clkmgr_stress_all 1.507m 12.407ms 48 50 96.00
V2 intr_test clkmgr_intr_test 1.110s 28.937us 50 50 100.00
V2 alert_test clkmgr_alert_test 43.018s 47 50 94.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 5.250s 317.604us 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 5.250s 317.604us 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 1.320s 22.305us 5 5 100.00
clkmgr_csr_rw 1.890s 180.181us 20 20 100.00
clkmgr_csr_aliasing 2.990s 124.975us 5 5 100.00
clkmgr_same_csr_outstanding 2.840s 465.699us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 1.320s 22.305us 5 5 100.00
clkmgr_csr_rw 1.890s 180.181us 20 20 100.00
clkmgr_csr_aliasing 2.990s 124.975us 5 5 100.00
clkmgr_same_csr_outstanding 2.840s 465.699us 20 20 100.00
V2 TOTAL 470 490 95.92
V2S tl_intg_err clkmgr_sec_cm 3.320s 282.139us 5 5 100.00
clkmgr_tl_intg_err 4.680s 320.926us 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 3.040s 120.389us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 3.040s 120.389us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 3.040s 120.389us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 3.040s 120.389us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 4.230s 670.204us 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 4.680s 320.926us 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 27.714s 48 50 96.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 41.737s 47 50 94.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 3.040s 120.389us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 42.577s 47 50 94.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 42.664s 46 50 92.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 33.512s 46 50 92.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 42.735s 46 50 92.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 42.816s 46 50 92.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 1.890s 180.181us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 3.320s 282.139us 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 1.890s 180.181us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 1.890s 180.181us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 3.320s 282.139us 5 5 100.00
V2S TOTAL 296 315 93.97
V3 regwen clkmgr_regwen 42.895s 48 50 96.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 3.055m 41.314ms 47 50 94.00
V3 TOTAL 95 100 95.00
TOTAL 963 1010 95.35

Testplan Progress

Items Total Written Passing Progress
V1 6 6 5 83.33
V2 11 11 3 27.27
V2S 9 9 4 44.44
V3 2 2 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.02 98.80

Failure Buckets

Past Results