FLASH_CTRL Simulation Results

Thursday May 23 2024 19:02:32 UTC

GitHub Revision: `1579f6a912`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 107680075914347604077716278187232582575581754843183664337576824686885697334979

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.856m	696.243us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.280s	20.701us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	46.390s	25.679us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.960s	63.597us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.323m	2.384ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	59.440s	1.902ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	19.500s	463.305us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.960s	63.597us	20	20	100.00
		flash_ctrl_csr_aliasing	59.440s	1.902ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.740s	16.898us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.840s	107.247us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.950s	20.097us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	1.513m	65.025us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	32.529m	188.129ms	3	3	100.00
		flash_ctrl_hw_rma_reset	16.637m	160.195ms	20	20	100.00
		flash_ctrl_lcmgr_intg	14.190s	15.040us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	40.639m	379.541ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	8.375m	3.354ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	3.416m	9.064ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.157h	306.172ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	3.068m	2.714ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	33.040s	273.863us	30	40	75.00
		flash_ctrl_rw_evict_all_en	32.880s	126.932us	36	40	90.00
		flash_ctrl_re_evict	40.550s	158.199us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	8.519m	772.033us	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	8.519m	772.033us	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	21.732m	23.090ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	30.170s	1.887ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	22.960m	497.036us	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	41.285m	4.542ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	16.499m	5.004ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	44.703m	3.217ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	13.780s	25.961us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.278m	2.787ms	4	5	80.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.820s	14.187us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.340s	15.369us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	14.782m	486.316us	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.301m	20.199ms	50	50	100.00
		flash_ctrl_otp_reset	2.263m	156.591us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	32.529m	188.129ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	5.424m	24.497ms	37	40	92.50
		flash_ctrl_intr_wr	1.280m	4.016ms	9	10	90.00
		flash_ctrl_intr_rd_slow_flash	7.360m	195.670ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	7.931m	290.739ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.621m	16.109ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.204m	993.077us	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	23.120s	21.644us	3	5	60.00
		flash_ctrl_ro_derr	2.530m	1.185ms	10	10	100.00
		flash_ctrl_rw_derr	11.836m	28.114ms	6	10	60.00
		flash_ctrl_derr_detect	1.758m	196.829us	5	5	100.00
		flash_ctrl_integrity	11.370m	3.775ms	4	5	80.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	22.870s	113.426us	5	5	100.00
		flash_ctrl_ro_serr	2.498m	4.105ms	10	10	100.00
		flash_ctrl_rw_serr	10.574m	49.686ms	7	10	70.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.267m	3.213ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.814m	1.016ms	5	5	100.00
V2	scramble	flash_ctrl_wo	4.274m	14.521ms	20	20	100.00
		flash_ctrl_write_word_sweep	15.180s	136.792us	1	1	100.00
		flash_ctrl_read_word_sweep	14.040s	74.150us	1	1	100.00
		flash_ctrl_ro	2.622m	1.494ms	19	20	95.00
		flash_ctrl_rw	10.863m	8.610ms	19	20	95.00
V2	filesystem_support	flash_ctrl_fs_sup	43.070s	1.360ms	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	22.073m	78.638ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.513m	10.012ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.890s	216.446us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	13.990s	58.190us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	20.490s	230.071us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	20.490s	230.071us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	46.390s	25.679us	5	5	100.00
		flash_ctrl_csr_rw	17.960s	63.597us	20	20	100.00
		flash_ctrl_csr_aliasing	59.440s	1.902ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	34.530s	114.275us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	46.390s	25.679us	5	5	100.00
		flash_ctrl_csr_rw	17.960s	63.597us	20	20	100.00
		flash_ctrl_csr_aliasing	59.440s	1.902ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	34.530s	114.275us	20	20	100.00
V2		TOTAL			982	1013	96.94
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.550s	27.940us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.550s	27.940us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.550s	27.940us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.550s	27.940us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.100s	13.818us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.329h	1.147ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.219m	1.567ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.219m	1.567ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.219m	1.567ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	32.590s	453.901us	3	3	100.00
		flash_ctrl_wr_intg	15.170s	164.539us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.856m	696.243us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.263m	156.591us	80	80	100.00
		flash_ctrl_disable	22.820s	14.187us	50	50	100.00
		flash_ctrl_sec_info_access	1.421m	23.835ms	50	50	100.00
		flash_ctrl_connect	16.340s	15.369us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	13.740s	21.112us	2	5	40.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.960s	63.597us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.550s	27.940us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.960s	63.597us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.550s	27.940us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.960s	63.597us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.550s	27.940us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.820s	14.187us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	32.590s	453.901us	3	3	100.00
		flash_ctrl_access_after_disable	14.490s	37.366us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.820s	14.187us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	30.170s	1.887ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	10.863m	8.610ms	19	20	95.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	10.574m	49.686ms	7	10	70.00
		flash_ctrl_rw_derr	11.836m	28.114ms	6	10	60.00
		flash_ctrl_integrity	11.370m	3.775ms	4	5	80.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	32.529m	188.129ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.329h	1.147ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.329h	1.147ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.329h	1.147ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.329h	1.147ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	23.020s	903.005us	4	5	80.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.140s	15.515us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.230s	21.618us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.329h	1.147ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.329h	1.147ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.329h	1.147ms	5	5	100.00
V2S		TOTAL			140	144	97.22
V3	asymmetric_read_path	flash_ctrl_rd_ooo	46.090s	220.363us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1243	1278	97.26

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	44	80.00
V2S	12	12	10	83.33
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.51	95.75	94.17	98.85	92.52	98.09	98.30	97.90

Failure Buckets

UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 14 failures:

Test flash_ctrl_rw_evict has 10 failures.

3.flash_ctrl_rw_evict.4870991232215196532636717924548576134866439349541306133932515508976150204323
Line 294, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_rw_evict/latest/run.log

  UVM_FATAL @ 42410.2 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x0001bf68
  UVM_INFO @ 42410.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

10.flash_ctrl_rw_evict.913585441699469273388638020416445558825202983722836979245742040991654768717
Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_rw_evict/latest/run.log

  UVM_FATAL @ 12227.3 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x0004ea70
  UVM_INFO @ 12227.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test flash_ctrl_rw_evict_all_en has 4 failures.

10.flash_ctrl_rw_evict_all_en.40000027154409364933132010100215497681212212855166076709585390346476826132794
Line 295, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_FATAL @ 32227.3 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x0001b0e8
  UVM_INFO @ 32227.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

22.flash_ctrl_rw_evict_all_en.9407415493690167482789986050870807547294885551664938953281746684000994431532
Line 296, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/22.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_FATAL @ 21276.5 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x000833b8
  UVM_INFO @ 21276.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:289) m_otf_scb [process_read] unexpected double bit error * has 5 failures:
- Test flash_ctrl_rw_derr has 3 failures.
  - 1.flash_ctrl_rw_derr.27180884999800051821737733307124682789302807668332701774495178993586985911851
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 2938348.9 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00040010
  UVM_INFO @ 2938348.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.flash_ctrl_rw_derr.51942968708025908805869279640945513262541777194561020944697117922878045846126
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 1065465.4 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00000200
  UVM_INFO @ 1065465.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test flash_ctrl_read_word_sweep_derr has 2 failures.
  - 2.flash_ctrl_read_word_sweep_derr.4436259346215540430494071930958063368300438387665380437274205211726481247812
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_read_word_sweep_derr/latest/run.log
```
  UVM_ERROR @ 5846.8 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x000009d8
  UVM_INFO @ 5846.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.flash_ctrl_read_word_sweep_derr.111925897440535668765056624927316230568688089185873385910681303866445423014883
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_read_word_sweep_derr/latest/run.log
```
  UVM_ERROR @ 78258.1 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00003a00
  UVM_INFO @ 78258.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 3 failures:
- Test flash_ctrl_config_regwen has 3 failures.
  - 0.flash_ctrl_config_regwen.72199695975895318664909292601092764620841719766270028054594877773447979133989
    Line 328, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_config_regwen/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_flash_ctrl_env_0.1/seq_lib/flash_ctrl_config_regwen_vseq.sv, 46
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - 1.flash_ctrl_config_regwen.38774931619500484099145995113465396310726373945940778257312521105443571238664
    Line 328, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_config_regwen/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_flash_ctrl_env_0.1/seq_lib/flash_ctrl_config_regwen_vseq.sv, 46
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - ... and 1 more failures.
Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 3 failures:
- Test flash_ctrl_rw_serr has 2 failures.
  - 4.flash_ctrl_rw_serr.64724030103910219087691862905442332154269264796424530830029675957474206213955
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw_serr/latest/run.log
```
  Job ID: smart:45eeb2d5-2b2d-4b2a-a3a5-40a40937040a
```
  - 6.flash_ctrl_rw_serr.51004317076584781615880063127016353810181600670672112040913905783834851015156
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_rw_serr/latest/run.log
```
  Job ID: smart:f1bf8b2d-67c1-4c1f-bcdf-37cddc03922c
```
- Test flash_ctrl_intr_wr has 1 failures.
  - 9.flash_ctrl_intr_wr.100876293836578385625934501412673067467993839623682438968625795425301539456103
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_intr_wr/latest/run.log
```
  Job ID: smart:1186a493-420c-46ed-8fbb-cd9c0b40a9c0
```
UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 2 failures:
- Test flash_ctrl_rw has 1 failures.
  - 1.flash_ctrl_rw.39244290888128431409035058412685194165653017640744535241292346451795140991993
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw/latest/run.log
```
  UVM_ERROR @ 75928.5 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 75928.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_ro has 1 failures.
  - 19.flash_ctrl_ro.57570596200994872032198027720951971642079571634404019775435552088988909016181
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/19.flash_ctrl_ro/latest/run.log
```
  UVM_ERROR @ 400596.6 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 400596.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 2 failures:

Test flash_ctrl_integrity has 1 failures.

3.flash_ctrl_integrity.73600789263663523803505135546508077478792118471567963497972204240519152656577
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_integrity/latest/run.log

  UVM_ERROR @ 14137309.7 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (58439306619259491787024 [0xc60004c018008092110] vs 39002257016307531792642 [0x842510c018489124102])
  UVM_INFO @ 14137309.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_rw_serr has 1 failures.

9.flash_ctrl_rw_serr.99159429993802856978112367968237209312969563320674584705430509935390239076865
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 1119558.8 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (56682815248407280515680 [0xc00c81516000b107a60] vs 66127548214146570943072 [0xe00c81516000b107a60])
  UVM_INFO @ 1119558.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 1 failures:
- Test flash_ctrl_rw_derr has 1 failures.
  - 0.flash_ctrl_rw_derr.45021364506294469919218283524933770120892485036768525047363487700494686731178
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 2374880.9 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (31734323166194790575445 [0x6b8523400010a002d55] vs 31734323166194790575441 [0x6b8523400010a002d51])
  UVM_INFO @ 2374880.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_otf_item.sv:247) [rd_scr] ecc error is detected has 1 failures:
- Test flash_ctrl_oversize_error has 1 failures.
  - 0.flash_ctrl_oversize_error.62118466946368357213805759070821836076776162555214129291359316641411011429823
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_oversize_error/latest/run.log
```
  UVM_ERROR @ 2953615.9 ns: (flash_otf_item.sv:247) [rd_scr] ecc error is detected
  UVM_INFO @ 2953615.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *fb2f17_3cf24a40:ffffffff_ffffffff mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 2.flash_ctrl_intr_rd.9674727080112493815147032656416457885315430332119042671248526124152078706409
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 1435033.8 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    1: obs:exp    79fb2f17_3cf24a40:ffffffff_ffffffff  mismatch!!
  UVM_INFO @ 1435033.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_err triggered unexpectedly has 1 failures:
- Test flash_ctrl_phy_arb_redun has 1 failures.
  - 3.flash_ctrl_phy_arb_redun.55237942795717284506656092061484424440607506966935963177012706010840818143977
    Line 302, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_phy_arb_redun/latest/run.log
```
  UVM_ERROR @ 21875.5 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_err triggered unexpectedly
  UVM_INFO @ 21875.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *c3a6610_bbd7ffe5:ffffffff_bbd7ffe* mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 15.flash_ctrl_intr_rd.72024983880282306666574802877467125118821113428487908442161985846922184577558
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/15.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 5622072.1 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    6: obs:exp    4c3a6610_bbd7ffe5:ffffffff_bbd7ffe5  mismatch!!
  UVM_INFO @ 5622072.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *a43d9b_a6bd6b68:ffffffff_a6bd6b* mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 28.flash_ctrl_intr_rd.2800318064067481849696697539686708900534055962824575596642082033216960007157
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/28.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 767902.3 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    4: obs:exp    10a43d9b_a6bd6b68:ffffffff_a6bd6b68  mismatch!!
  UVM_INFO @ 767902.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```