FLASH_CTRL Simulation Results

Sunday May 26 2024 19:04:10 UTC

GitHub Revision: `2cf28c40e5`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 76231542290686940289653487239061276463019235878731279188279352215076078972419

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.639m	211.083us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	27.000s	27.071us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	39.320s	41.407us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.710s	157.920us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.463m	12.920ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	51.510s	1.709ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	19.090s	82.491us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.710s	157.920us	20	20	100.00
		flash_ctrl_csr_aliasing	51.510s	1.709ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.770s	25.282us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.660s	52.337us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.980s	84.688us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	1.529m	348.953us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	36.462m	155.047ms	3	3	100.00
		flash_ctrl_hw_rma_reset	22.098m	480.369ms	20	20	100.00
		flash_ctrl_lcmgr_intg	14.200s	26.494us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	45.986m	250.176ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	10.700m	4.088ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	4.206m	12.032ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.093h	54.786ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	3.342m	5.653ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	32.370s	47.239us	30	40	75.00
		flash_ctrl_rw_evict_all_en	32.710s	140.230us	34	40	85.00
		flash_ctrl_re_evict	40.230s	140.437us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	9.743m	2.585ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	9.743m	2.585ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	19.460m	69.747ms	19	20	95.00
V2	fetch_code	flash_ctrl_fetch_code	32.020s	3.727ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	18.222m	1.836ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	42.056m	9.242ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	16.841m	1.010ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	52.993m	16.761ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	14.290s	45.221us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.606m	2.483ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.800s	28.204us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.690s	14.911us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	17.070m	231.085us	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.462m	3.315ms	50	50	100.00
		flash_ctrl_otp_reset	2.306m	136.585us	79	80	98.75
V2	isolation_partition	flash_ctrl_hw_rma	36.462m	155.047ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	4.522m	3.271ms	37	40	92.50
		flash_ctrl_intr_wr	1.466m	30.071ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	8.678m	48.812ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	7.661m	290.128ms	9	10	90.00
V2	invalid_op	flash_ctrl_invalid_op	1.573m	4.924ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.227m	2.072ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	23.620s	34.147us	5	5	100.00
		flash_ctrl_ro_derr	3.040m	682.770us	10	10	100.00
		flash_ctrl_rw_derr	11.962m	5.908ms	8	10	80.00
		flash_ctrl_derr_detect	1.808m	208.584us	5	5	100.00
		flash_ctrl_integrity	12.014m	6.059ms	2	5	40.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	23.370s	152.676us	4	5	80.00
		flash_ctrl_ro_serr	2.807m	2.602ms	10	10	100.00
		flash_ctrl_rw_serr	11.226m	5.569ms	9	10	90.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.328m	685.379us	4	5	80.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.717m	8.607ms	5	5	100.00
V2	scramble	flash_ctrl_wo	4.229m	3.047ms	20	20	100.00
		flash_ctrl_write_word_sweep	15.830s	390.339us	1	1	100.00
		flash_ctrl_read_word_sweep	14.460s	83.868us	1	1	100.00
		flash_ctrl_ro	2.573m	493.656us	19	20	95.00
		flash_ctrl_rw	12.231m	34.050ms	19	20	95.00
V2	filesystem_support	flash_ctrl_fs_sup	43.360s	338.874us	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	18.298m	211.538ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	2.498m	10.012ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	15.400s	454.279us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.150s	18.344us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	20.550s	236.202us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	20.550s	236.202us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	39.320s	41.407us	5	5	100.00
		flash_ctrl_csr_rw	17.710s	157.920us	20	20	100.00
		flash_ctrl_csr_aliasing	51.510s	1.709ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.810s	239.458us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	39.320s	41.407us	5	5	100.00
		flash_ctrl_csr_rw	17.710s	157.920us	20	20	100.00
		flash_ctrl_csr_aliasing	51.510s	1.709ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.810s	239.458us	20	20	100.00
V2		TOTAL			981	1013	96.84
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.340s	11.565us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.340s	11.565us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.340s	11.565us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.340s	11.565us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.350s	13.748us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.355h	1.561ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.096m	1.215ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.096m	1.215ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.096m	1.215ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	32.690s	706.165us	3	3	100.00
		flash_ctrl_wr_intg	15.700s	83.646us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.639m	211.083us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.306m	136.585us	79	80	98.75
		flash_ctrl_disable	22.800s	28.204us	50	50	100.00
		flash_ctrl_sec_info_access	1.418m	11.436ms	50	50	100.00
		flash_ctrl_connect	16.690s	14.911us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	13.890s	20.999us	3	5	60.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.710s	157.920us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.340s	11.565us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.710s	157.920us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.340s	11.565us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.710s	157.920us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.340s	11.565us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.800s	28.204us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	32.690s	706.165us	3	3	100.00
		flash_ctrl_access_after_disable	14.180s	13.780us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.800s	28.204us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	32.020s	3.727ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	12.231m	34.050ms	19	20	95.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	11.226m	5.569ms	9	10	90.00
		flash_ctrl_rw_derr	11.962m	5.908ms	8	10	80.00
		flash_ctrl_integrity	12.014m	6.059ms	2	5	40.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	36.462m	155.047ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.355h	1.561ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.355h	1.561ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.355h	1.561ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.355h	1.561ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	21.940s	625.871us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	15.210s	27.004us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.270s	15.060us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.355h	1.561ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.355h	1.561ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.355h	1.561ms	5	5	100.00
V2S		TOTAL			142	144	98.61
V3	asymmetric_read_path	flash_ctrl_rd_ooo	46.670s	101.578us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1244	1278	97.34

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	42	76.36
V2S	12	12	11	91.67
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.24	95.31	94.12	98.85	92.52	97.02	98.01	97.81

Failure Buckets

UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 15 failures:

Test flash_ctrl_rw_evict has 10 failures.

1.flash_ctrl_rw_evict.32626134624016359733970601876844950948428913610724909396369084115370580466587
Line 286, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_evict/latest/run.log

  UVM_FATAL @ 47239.1 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00082110
  UVM_INFO @ 47239.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.flash_ctrl_rw_evict.61239218789486391219362885499808188880753923147743240493447514050155720410640
Line 289, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_rw_evict/latest/run.log

  UVM_FATAL @ 8304.8 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00000018
  UVM_INFO @ 8304.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test flash_ctrl_rw_evict_all_en has 5 failures.

7.flash_ctrl_rw_evict_all_en.66479385653774454940205284631438992309463143928719128405577074643939343178062
Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_FATAL @ 12369.4 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00091858
  UVM_INFO @ 12369.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

15.flash_ctrl_rw_evict_all_en.74586330476506680398974197440064174010834142001928740415738467722063175271042
Line 296, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/15.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_FATAL @ 58181.5 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x000af030
  UVM_INFO @ 58181.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 3 failures:

Test flash_ctrl_rw_serr has 1 failures.

1.flash_ctrl_rw_serr.45904880217192260238561951201471422431030129143344891709774036769589848936718
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 4380642.3 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (38960766917007739273360 [0x840114190074d414090] vs 38960911032195815129232 [0x840134190074d414090])
  UVM_INFO @ 4380642.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_integrity has 1 failures.

3.flash_ctrl_integrity.99484914222780522459634279616485906363396578605276425712998807159648667895476
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_integrity/latest/run.log

  UVM_ERROR @ 2771450.8 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (606580974635723612802 [0x20e20086a0a0896282] vs 38667114050745631506466 [0x83026010200b1080022])
  UVM_INFO @ 2771450.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_rw_derr has 1 failures.

7.flash_ctrl_rw_derr.53712542318050125383951575105092422137614700436189365545730743586571540993031
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_rw_derr/latest/run.log

  UVM_ERROR @ 14527040.2 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (23796669818757849295235 [0x50a0522600000d02983] vs 23796669818757849295234 [0x50a0522600000d02982])
  UVM_INFO @ 14527040.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 3 failures:

Test flash_ctrl_serr_counter has 1 failures.

1.flash_ctrl_serr_counter.51934292924515474643830303637908090485836029323103744902709875857050650796179
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_serr_counter/latest/run.log

  UVM_ERROR @ 114800.0 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 114800.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_ro has 1 failures.

12.flash_ctrl_ro.75607691975128293987017412286395707002605229024805440987800236834218849682749
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_ro/latest/run.log

  UVM_ERROR @ 655688.7 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 655688.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_rw has 1 failures.

17.flash_ctrl_rw.2314640108268314547236762208255214121091233048708848895544373476396846855637
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/17.flash_ctrl_rw/latest/run.log

  UVM_ERROR @ 1545571.1 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 1545571.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Error-[CNST-CIF] Constraints inconsistency failure has 2 failures:
- Test flash_ctrl_config_regwen has 2 failures.
  - 0.flash_ctrl_config_regwen.11195038574703974986126885356815620548165691979852640613288658239998996097707
    Line 328, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_config_regwen/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_flash_ctrl_env_0.1/seq_lib/flash_ctrl_config_regwen_vseq.sv, 46
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - 1.flash_ctrl_config_regwen.101198947135503198493415222086309134463173780348895951154203297915902517071708
    Line 328, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_config_regwen/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_flash_ctrl_env_0.1/seq_lib/flash_ctrl_config_regwen_vseq.sv, 46
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:289) m_otf_scb [process_read] unexpected double bit error * has 1 failures:
- Test flash_ctrl_integrity has 1 failures.
  - 0.flash_ctrl_integrity.42281010422198088593198094755702822650818977484707283749910756765535475888345
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_integrity/latest/run.log
```
  UVM_ERROR @ 11353878.4 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00003c00
  UVM_INFO @ 11353878.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 1 failures:
- Test flash_ctrl_integrity has 1 failures.
  - 2.flash_ctrl_integrity.85893147720314682636548683774607387019323943271082937351170713825358360225250
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_integrity/latest/run.log
```
  UVM_ERROR @ 2105141.1 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (4722372241602061329536 [0x100001475896004e480] vs 5017587013136536630276 [0x11001020421e084f404])
  UVM_INFO @ 2105141.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_err triggered unexpectedly has 1 failures:
- Test flash_ctrl_read_word_sweep_serr has 1 failures.
  - 3.flash_ctrl_read_word_sweep_serr.6724024994133099076331952351406761288006010660493820413163519096159320290656
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_read_word_sweep_serr/latest/run.log
```
  UVM_ERROR @ 5146.4 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_err triggered unexpectedly
  UVM_INFO @ 5146.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 1 failures:
- Test flash_ctrl_intr_wr_slow_flash has 1 failures.
  - 3.flash_ctrl_intr_wr_slow_flash.59200170882661653804519819379770893954745416796193700647048279821657731223222
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_intr_wr_slow_flash/latest/run.log
```
  Job ID: smart:c854eb21-a0cd-402f-933f-02615af7f2de
```
UVM_ERROR (flash_ctrl_otf_base_vseq.sv:362) [flash_ctrl_rw_vseq] Check failed (*) Too many unsuccessful attempts to create a prog_op has 1 failures:
- Test flash_ctrl_rw_derr has 1 failures.
  - 5.flash_ctrl_rw_derr.68202038189598231219372552363881940514559093278198853617028373573714803639701
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 7237531.4 ns: (flash_ctrl_otf_base_vseq.sv:362) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_vseq] Check failed (0) Too many unsuccessful attempts to create a prog_op
  UVM_INFO @ 7237531.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 1 failures:
- Test flash_ctrl_rw_evict_all_en has 1 failures.
  - 8.flash_ctrl_rw_evict_all_en.750917861669493258370592460496686394196549317411584932660641619701749987256
    Line 288, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_rw_evict_all_en/latest/run.log
```
  UVM_ERROR @ 15916.4 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 15916.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp cb876466_be246b09:ffffffff_ffffffff mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 12.flash_ctrl_intr_rd.110667799969095074149678900543778897538536467183505917015289825614393617274217
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 1226203.5 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    5: obs:exp    cb876466_be246b09:ffffffff_ffffffff  mismatch!!
  UVM_INFO @ 1226203.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (flash_ctrl_mp_regions_vseq.sv:196) [flash_ctrl_mp_regions_vseq] wait timeout for alert_count == exp_alertcnt after do_mp_reg() alert_cnt:* exp_alert_cnt:* has 1 failures:
- Test flash_ctrl_mp_regions has 1 failures.
  - 15.flash_ctrl_mp_regions.69519503671372600379796787309948336228481633563904668446468828088835633062311
    Line 906, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/15.flash_ctrl_mp_regions/latest/run.log
```
  UVM_FATAL @ 690907.2 ns: (flash_ctrl_mp_regions_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.flash_ctrl_mp_regions_vseq] wait timeout for alert_count == exp_alertcnt after do_mp_reg() alert_cnt:36  exp_alert_cnt:37
  UVM_INFO @ 690907.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp bb26ce41_9b7c6a61:ffffffff_ffffffff mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 22.flash_ctrl_intr_rd.44200903196444370668246015253316886049962529858509871526860020763815441858355
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/22.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 1490734.7 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    7: obs:exp    bb26ce41_9b7c6a61:ffffffff_ffffffff  mismatch!!
  UVM_INFO @ 1490734.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp c73e9081_a895f345:ffffffff_a895f* mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 28.flash_ctrl_intr_rd.59765688168251733103188109140201669712631358531990017086356402687484375932611
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/28.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 394875.5 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    5: obs:exp    c73e9081_a895f345:ffffffff_a895f345  mismatch!!
  UVM_INFO @ 394875.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending 'dst_req_o' has 1 failures:
- Test flash_ctrl_otp_reset has 1 failures.
  - 56.flash_ctrl_otp_reset.27083181249726164542797776458174979957627152732604499263460705359164352150347
    Line 387, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/56.flash_ctrl_otp_reset/latest/run.log
```
      Offending 'dst_req_o'
  UVM_ERROR @ 43824.3 ns: (prim_sync_reqack.sv:354) [ASSERT FAILED] SyncReqAckAckNeedsReq
  UVM_INFO @ 43824.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```