FLASH_CTRL Simulation Results

Tuesday May 28 2024 19:30:06 UTC

GitHub Revision: `0e5093d709`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 51604449886868634540233838791789448907774502353938218657919214072353062987195

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.324m	2.469ms	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.580s	27.048us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	46.040s	183.126us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.700s	204.858us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.452m	30.925ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.069m	3.277ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	19.620s	754.243us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.700s	204.858us	20	20	100.00
		flash_ctrl_csr_aliasing	1.069m	3.277ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.760s	53.865us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.490s	16.369us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.970s	23.070us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	1.869m	61.089us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	32.709m	174.152ms	3	3	100.00
		flash_ctrl_hw_rma_reset	23.775m	760.540ms	20	20	100.00
		flash_ctrl_lcmgr_intg	13.950s	56.465us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	47.767m	284.775ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	8.230m	2.809ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	3.265m	4.870ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.083h	203.464ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.472m	1.533ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	32.420s	55.890us	33	40	82.50
		flash_ctrl_rw_evict_all_en	32.070s	31.565us	37	40	92.50
		flash_ctrl_re_evict	37.990s	662.915us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	9.522m	2.123ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	9.522m	2.123ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	16.878m	12.668ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	28.270s	830.327us	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	22.699m	535.652us	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	45.258m	30.456ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	18.344m	949.079us	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	56.594m	4.125ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	14.070s	25.411us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.597m	3.444ms	4	5	80.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.870s	78.511us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.570s	23.120us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	23.222m	457.691us	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.596m	13.089ms	50	50	100.00
		flash_ctrl_otp_reset	2.281m	48.960us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	32.709m	174.152ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	4.537m	1.764ms	39	40	97.50
		flash_ctrl_intr_wr	1.456m	10.010ms	9	10	90.00
		flash_ctrl_intr_rd_slow_flash	8.152m	68.796ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	4.292m	83.992ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.622m	19.352ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.239m	2.924ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	23.280s	31.790us	4	5	80.00
		flash_ctrl_ro_derr	2.877m	788.736us	10	10	100.00
		flash_ctrl_rw_derr	11.222m	13.143ms	7	10	70.00
		flash_ctrl_derr_detect	1.789m	116.283us	5	5	100.00
		flash_ctrl_integrity	10.757m	4.477ms	2	5	40.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	22.860s	62.343us	3	5	60.00
		flash_ctrl_ro_serr	2.702m	9.773ms	10	10	100.00
		flash_ctrl_rw_serr	11.633m	22.365ms	7	10	70.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.500m	933.429us	4	5	80.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.504m	853.152us	5	5	100.00
V2	scramble	flash_ctrl_wo	3.995m	17.844ms	19	20	95.00
		flash_ctrl_write_word_sweep	14.720s	253.590us	1	1	100.00
		flash_ctrl_read_word_sweep	14.490s	23.970us	1	1	100.00
		flash_ctrl_ro	2.106m	2.231ms	19	20	95.00
		flash_ctrl_rw	11.012m	17.165ms	18	20	90.00
V2	filesystem_support	flash_ctrl_fs_sup	43.490s	2.244ms	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	20.507m	77.495ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.291m	10.013ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.690s	72.425us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.070s	44.243us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	20.040s	402.163us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	20.040s	402.163us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	46.040s	183.126us	5	5	100.00
		flash_ctrl_csr_rw	17.700s	204.858us	20	20	100.00
		flash_ctrl_csr_aliasing	1.069m	3.277ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	37.220s	4.030ms	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	46.040s	183.126us	5	5	100.00
		flash_ctrl_csr_rw	17.700s	204.858us	20	20	100.00
		flash_ctrl_csr_aliasing	1.069m	3.277ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	37.220s	4.030ms	20	20	100.00
V2		TOTAL			983	1013	97.04
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.370s	30.754us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.370s	30.754us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.370s	30.754us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.370s	30.754us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.130s	15.091us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.357h	3.072ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.434m	4.311ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.434m	4.311ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.434m	4.311ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	31.820s	62.951us	3	3	100.00
		flash_ctrl_wr_intg	15.000s	218.275us	2	3	66.67
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.324m	2.469ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.281m	48.960us	80	80	100.00
		flash_ctrl_disable	22.870s	78.511us	50	50	100.00
		flash_ctrl_sec_info_access	1.400m	798.509us	50	50	100.00
		flash_ctrl_connect	16.570s	23.120us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.130s	143.358us	2	5	40.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.700s	204.858us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.370s	30.754us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.700s	204.858us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.370s	30.754us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.700s	204.858us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.370s	30.754us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.870s	78.511us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	31.820s	62.951us	3	3	100.00
		flash_ctrl_access_after_disable	14.020s	49.593us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.870s	78.511us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	28.270s	830.327us	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	11.012m	17.165ms	18	20	90.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	11.633m	22.365ms	7	10	70.00
		flash_ctrl_rw_derr	11.222m	13.143ms	7	10	70.00
		flash_ctrl_integrity	10.757m	4.477ms	2	5	40.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	32.709m	174.152ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.357h	3.072ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.357h	3.072ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.357h	3.072ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.357h	3.072ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	23.860s	915.842us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.370s	16.049us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	28.480s	2.921ms	4	5	80.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.357h	3.072ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.357h	3.072ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.357h	3.072ms	5	5	100.00
V2S		TOTAL			139	144	96.53
V3	asymmetric_read_path	flash_ctrl_rd_ooo	42.640s	47.499us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1243	1278	97.26

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	41	74.55
V2S	12	12	9	75.00
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.49	95.85	94.24	98.85	91.84	98.29	98.21	98.18

Failure Buckets

UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 8 failures:

Test flash_ctrl_rw_evict has 6 failures.

2.flash_ctrl_rw_evict.106061866529338574500656452031591309722059593610823556853427481484677362727138
Line 298, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rw_evict/latest/run.log

  UVM_FATAL @ 52026.0 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00036790
  UVM_INFO @ 52026.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

16.flash_ctrl_rw_evict.21605771350227478404927206981398963843313283339737881611076034888028089615406
Line 289, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/16.flash_ctrl_rw_evict/latest/run.log

  UVM_FATAL @ 9102.3 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00093700
  UVM_INFO @ 9102.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test flash_ctrl_rw_evict_all_en has 2 failures.

12.flash_ctrl_rw_evict_all_en.73600785002780954980889488866242870245604544029320208848124780768624192936431
Line 295, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_FATAL @ 13674.1 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00039aa8
  UVM_INFO @ 13674.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

31.flash_ctrl_rw_evict_all_en.1284794795170884363805422277573015661790232418978490819971011048510887498556
Line 300, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/31.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_FATAL @ 30214.1 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x000bcb10
  UVM_INFO @ 30214.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 5 failures:

Test flash_ctrl_integrity has 2 failures.

0.flash_ctrl_integrity.44933001173045502331944378308508224819801475990798907290519079079826236238235
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_integrity/latest/run.log

  UVM_ERROR @ 2171586.0 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (19517808715287539089424 [0x422100200c581060010] vs 38378559202738029199426 [0x82081804091a3100042])
  UVM_INFO @ 2171586.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.flash_ctrl_integrity.100985118302575777704469476534329455387341381318525619084577032450396573778890
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_integrity/latest/run.log

  UVM_ERROR @ 3512910.4 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (11954139283426883413253 [0x288090226884a042505] vs 171208879176944370560 [0x948002082068ac380])
  UVM_INFO @ 3512910.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_serr_counter has 1 failures.

1.flash_ctrl_serr_counter.58621467605530757081446912442142639466888860959949142413136976253637029931657
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_serr_counter/latest/run.log

  UVM_ERROR @ 1485826.3 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (18996123555828736460812 [0x405c82c00400a14080c] vs 18996123555966175414284 [0x405c82c00600a14080c])
  UVM_INFO @ 1485826.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_rw_serr has 2 failures.

7.flash_ctrl_rw_serr.58486744488292878130275118596992724808689722392140057558081895595674069610952
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 4335187.3 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (1154786796287595824 [0x1006a07910089530] vs 1154786796824466736 [0x1006a07930089530])
  UVM_INFO @ 4335187.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.flash_ctrl_rw_serr.7037498338282369551590236219808356803772995240130861345568650451988689395981
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 263554.8 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (742481450341199253840 [0x284000014000041150] vs 751704822378054029648 [0x28c000014000041150])
  UVM_INFO @ 263554.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 4 failures:
- Test flash_ctrl_rw has 1 failures.
  - 0.flash_ctrl_rw.80574511048483171355147021339414896156879066292772156160060092420261161624505
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw/latest/run.log
```
  Job ID: smart:c9100a09-4736-4092-8322-edd7ae6068f4
```
- Test flash_ctrl_oversize_error has 1 failures.
  - 3.flash_ctrl_oversize_error.101240746616078473229458127600893858469383320654794681829882076680613795074648
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_oversize_error/latest/run.log
```
  Job ID: smart:a3f7451f-1ad7-43ab-b0ce-710a427241c1
```
- Test flash_ctrl_intr_wr has 1 failures.
  - 8.flash_ctrl_intr_wr.55318148856552172296272506382941491571801809516720428619514728914233167129116
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_intr_wr/latest/run.log
```
  Job ID: smart:8784590a-8c6c-44e3-aedd-6902fdcdc9dd
```
- Test flash_ctrl_wo has 1 failures.
  - 9.flash_ctrl_wo.21093199330405790145504420869679824748875197425566758143010449645368654220157
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_wo/latest/run.log
```
  Job ID: smart:9096a69b-021f-4eb1-82c7-18f342f3dee2
```

UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 4 failures:

Test flash_ctrl_read_word_sweep_serr has 1 failures.

0.flash_ctrl_read_word_sweep_serr.41459182380285794364118136126867514378276413141072755278515161430427032175579
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_read_word_sweep_serr/latest/run.log

  UVM_ERROR @ 5644.3 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 5644.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_rw_serr has 1 failures.

3.flash_ctrl_rw_serr.78748107787203508563500870048505963238883995297697839348487442478555079991601
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 5949870.3 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 5949870.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_ro has 1 failures.

6.flash_ctrl_ro.65100738688851199284651234902010695441267928000453626494558905383273456395816
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_ro/latest/run.log

  UVM_ERROR @ 107362.1 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 107362.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_rw has 1 failures.

6.flash_ctrl_rw.23700456285249078114129255592127205042013155948448777167493374943697432275881
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_rw/latest/run.log

  UVM_ERROR @ 310857.1 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 310857.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:289) m_otf_scb [process_read] unexpected double bit error * has 3 failures:
- Test flash_ctrl_read_word_sweep_derr has 1 failures.
  - 0.flash_ctrl_read_word_sweep_derr.58206117565002806243744747931447812249031139986371489603572794178687660139742
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_read_word_sweep_derr/latest/run.log
```
  UVM_ERROR @ 21224.9 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x0001e520
  UVM_INFO @ 21224.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_integrity has 1 failures.
  - 2.flash_ctrl_integrity.55504882483368873722640809997395329304635722451623617719867935478463067296070
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_integrity/latest/run.log
```
  UVM_ERROR @ 2735678.1 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00003e00
  UVM_INFO @ 2735678.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_rw_derr has 1 failures.
  - 7.flash_ctrl_rw_derr.112844988139843643324294867673490615204574277522881509732607567146860054458866
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 5200112.1 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00003200
  UVM_INFO @ 5200112.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 3 failures:
- Test flash_ctrl_config_regwen has 3 failures.
  - 0.flash_ctrl_config_regwen.101703443704338955202269044760240770035581082085926714249792857788214453269845
    Line 328, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_config_regwen/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_flash_ctrl_env_0.1/seq_lib/flash_ctrl_config_regwen_vseq.sv, 46
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - 3.flash_ctrl_config_regwen.114791582863494228404063433096706795664350595870640650534311004617883903037594
    Line 328, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_config_regwen/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_flash_ctrl_env_0.1/seq_lib/flash_ctrl_config_regwen_vseq.sv, 46
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - ... and 1 more failures.

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 2 failures:

Test flash_ctrl_rw_derr has 2 failures.

3.flash_ctrl_rw_derr.62312396621420425696344718193121135497593115498347915465837260237821466336533
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_rw_derr/latest/run.log

  UVM_ERROR @ 10662142.2 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (37782602587201566433384 [0x80032f1084080286068] vs 37782602587201566425192 [0x80032f1084080284068])
  UVM_INFO @ 10662142.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.flash_ctrl_rw_derr.25525478891642124978248724035823384150428188704167523249744254545932381606997
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw_derr/latest/run.log

  UVM_ERROR @ 3483780.5 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (60886199208408788246933 [0xce4a5c0c7238bb02195] vs 60886199208408779858325 [0xce4a5c0c7238b302195])
  UVM_INFO @ 3483780.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:367) [wdata_page0_comp_bank1] *: obs:exp d9_*_cce32fc2_3a80a275:*_*_7128f444_10004f* mismatch!! has 1 failures:
- Test flash_ctrl_wr_intg has 1 failures.
  - 0.flash_ctrl_wr_intg.16333606026084416004219947746306087310531430048540148850818526728639725676667
    Line 294, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_wr_intg/latest/run.log
```
  UVM_ERROR @ 32098.2 ns: (flash_ctrl_otf_scoreboard.sv:367) [wdata_page0_comp_bank1]    0: obs:exp    d9_1_cce32fc2_3a80a275:29_1_7128f444_10004f38  mismatch!!
  UVM_INFO @ 32098.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_otf_item.sv:247) [rd_scr] ecc error is detected has 1 failures:
- Test flash_ctrl_read_word_sweep_serr has 1 failures.
  - 2.flash_ctrl_read_word_sweep_serr.16676889305893145058910057799444181099941633364945615566874697857882663381311
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_read_word_sweep_serr/latest/run.log
```
  UVM_ERROR @ 14947.9 ns: (flash_otf_item.sv:247) [rd_scr] ecc error is detected
  UVM_INFO @ 14947.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_err did not trigger max_delay:* has 1 failures:
- Test flash_ctrl_phy_ack_consistency has 1 failures.
  - 4.flash_ctrl_phy_ack_consistency.108693373871846220939011943330901617354066340791200364835310551934242219945291
    Line 284, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_phy_ack_consistency/latest/run.log
```
  UVM_ERROR @ 2920763.9 ns: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_err did not trigger max_delay:20000
  UVM_INFO @ 2920763.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *bec196d_770d0e5a:ffffffff_770d0e5a mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 27.flash_ctrl_intr_rd.16517920540508687734605574404115466612257307737781940105428065628100364089355
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/27.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 6893563.2 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    0: obs:exp    5bec196d_770d0e5a:ffffffff_770d0e5a  mismatch!!
  UVM_INFO @ 6893563.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: * has 1 failures:
- Test flash_ctrl_rw_evict has 1 failures.
  - 32.flash_ctrl_rw_evict.33949746054828869904438342462019110709957447622955497252173021246703242186126
    Line 297, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/32.flash_ctrl_rw_evict/latest/run.log
```
  UVM_ERROR @ 12857.4 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: 0x0
  UVM_INFO @ 12857.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 1 failures:
- Test flash_ctrl_rw_evict_all_en has 1 failures.
  - 35.flash_ctrl_rw_evict_all_en.107530263274749385762116749340848396571913744155831345033471127350094665772320
    Line 290, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/35.flash_ctrl_rw_evict_all_en/latest/run.log
```
  UVM_ERROR @ 21225.7 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 21225.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```