FLASH_CTRL Simulation Results

Thursday May 30 2024 19:02:59 UTC

GitHub Revision: `8cb25a6867`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 26638040090898561482658723926798947801831709189350919955228328310045202344042

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.667m	1.412ms	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.150s	16.802us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	46.970s	125.215us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.580s	469.726us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.189m	2.844ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	53.950s	1.805ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	19.960s	176.818us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.580s	469.726us	20	20	100.00
		flash_ctrl_csr_aliasing	53.950s	1.805ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.630s	53.614us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.850s	34.988us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.880s	21.943us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	1.710m	208.698us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	32.097m	186.786ms	3	3	100.00
		flash_ctrl_hw_rma_reset	16.440m	160.189ms	20	20	100.00
		flash_ctrl_lcmgr_intg	13.780s	138.866us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	48.586m	243.419ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	7.582m	2.863ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	3.459m	18.827ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.143h	143.804ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.473m	719.786us	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	31.520s	44.993us	25	40	62.50
		flash_ctrl_rw_evict_all_en	32.010s	101.541us	34	40	85.00
		flash_ctrl_re_evict	38.300s	438.402us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	10.022m	17.014ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	10.022m	17.014ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	13.569m	49.473ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	27.300s	604.325us	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	21.860m	1.512ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	43.802m	13.068ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	16.089m	707.052us	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	48.376m	673.960us	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	14.030s	47.113us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.608m	6.340ms	4	5	80.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.630s	11.019us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.550s	15.783us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	25.141m	354.544us	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.488m	12.331ms	50	50	100.00
		flash_ctrl_otp_reset	2.265m	71.116us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	32.097m	186.786ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	3.885m	11.894ms	37	40	92.50
		flash_ctrl_intr_wr	1.446m	18.166ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	6.448m	99.483ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	4.471m	343.713ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.535m	4.029ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.245m	5.139ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	22.240s	58.335us	3	5	60.00
		flash_ctrl_ro_derr	2.599m	6.040ms	10	10	100.00
		flash_ctrl_rw_derr	13.477m	4.903ms	8	10	80.00
		flash_ctrl_derr_detect	1.753m	121.542us	5	5	100.00
		flash_ctrl_integrity	11.167m	9.459ms	3	5	60.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	22.560s	25.731us	5	5	100.00
		flash_ctrl_ro_serr	2.658m	1.325ms	10	10	100.00
		flash_ctrl_rw_serr	11.449m	14.704ms	7	10	70.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.727m	2.283ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.488m	854.682us	5	5	100.00
V2	scramble	flash_ctrl_wo	3.692m	12.105ms	19	20	95.00
		flash_ctrl_write_word_sweep	15.400s	139.130us	1	1	100.00
		flash_ctrl_read_word_sweep	13.620s	80.194us	1	1	100.00
		flash_ctrl_ro	2.232m	5.666ms	18	20	90.00
		flash_ctrl_rw	10.035m	4.955ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	40.960s	681.680us	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	20.329m	71.758ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	4.699m	10.013ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.300s	196.904us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.230s	49.742us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	20.270s	444.713us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	20.270s	444.713us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	46.970s	125.215us	5	5	100.00
		flash_ctrl_csr_rw	17.580s	469.726us	20	20	100.00
		flash_ctrl_csr_aliasing	53.950s	1.805ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.340s	324.814us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	46.970s	125.215us	5	5	100.00
		flash_ctrl_csr_rw	17.580s	469.726us	20	20	100.00
		flash_ctrl_csr_aliasing	53.950s	1.805ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.340s	324.814us	20	20	100.00
V2		TOTAL			976	1013	96.35
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.120s	18.060us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.120s	18.060us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.120s	18.060us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.120s	18.060us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.440s	29.132us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.323h	2.007ms	5	5	100.00
		flash_ctrl_tl_intg_err	14.977m	4.221ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	14.977m	4.221ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	14.977m	4.221ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	31.770s	153.595us	3	3	100.00
		flash_ctrl_wr_intg	15.850s	178.159us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.667m	1.412ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.265m	71.116us	80	80	100.00
		flash_ctrl_disable	22.630s	11.019us	50	50	100.00
		flash_ctrl_sec_info_access	1.559m	4.050ms	50	50	100.00
		flash_ctrl_connect	16.550s	15.783us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	13.810s	75.038us	2	5	40.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.580s	469.726us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.120s	18.060us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.580s	469.726us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.120s	18.060us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.580s	469.726us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.120s	18.060us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.630s	11.019us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	31.770s	153.595us	3	3	100.00
		flash_ctrl_access_after_disable	13.750s	20.439us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.630s	11.019us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	27.300s	604.325us	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	10.035m	4.955ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	11.449m	14.704ms	7	10	70.00
		flash_ctrl_rw_derr	13.477m	4.903ms	8	10	80.00
		flash_ctrl_integrity	11.167m	9.459ms	3	5	60.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	32.097m	186.786ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.323h	2.007ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.323h	2.007ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.323h	2.007ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.323h	2.007ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	21.070s	886.220us	4	5	80.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.420s	48.385us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.100s	43.964us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.323h	2.007ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.323h	2.007ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.323h	2.007ms	5	5	100.00
V2S		TOTAL			140	144	97.22
V3	asymmetric_read_path	flash_ctrl_rd_ooo	42.760s	47.362us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1237	1278	96.79

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	45	81.82
V2S	12	12	10	83.33
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.21	95.31	93.96	98.85	92.52	97.00	98.01	97.84

Failure Buckets

UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 21 failures:

Test flash_ctrl_rw_evict has 15 failures.

0.flash_ctrl_rw_evict.82215710995374531292585790349628651746568477818906194715382136322325468204396
Line 300, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_evict/latest/run.log

  UVM_FATAL @ 20552.4 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00031ee0
  UVM_INFO @ 20552.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.flash_ctrl_rw_evict.76536839202728404283815748661434644223635190707939898362403343799488329131251
Line 301, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_evict/latest/run.log

  UVM_FATAL @ 29253.6 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x000bfe68
  UVM_INFO @ 29253.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 13 more failures.

Test flash_ctrl_rw_evict_all_en has 6 failures.

13.flash_ctrl_rw_evict_all_en.67751779950922702123503991036078133043489838691822400508412270765839091407800
Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_FATAL @ 9618.0 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x000388b8
  UVM_INFO @ 9618.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

17.flash_ctrl_rw_evict_all_en.41766323228489384501170066327069601037822592867639266864495253545485164228356
Line 300, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/17.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_FATAL @ 210566.7 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00002a40
  UVM_INFO @ 210566.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 6 failures:

Test flash_ctrl_integrity has 2 failures.

0.flash_ctrl_integrity.78216074331660251048989984426252622454236333789009121852865123867980547488119
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_integrity/latest/run.log

  UVM_ERROR @ 10130087.5 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (149163864348082350826 [0x8161080521000aaea] vs 519037151431213756600 [0x1c231663400020b0b8])
  UVM_INFO @ 10130087.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.flash_ctrl_integrity.56687083776826207974980931480149178594309712674008436457442491544604471894086
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_integrity/latest/run.log

  UVM_ERROR @ 6453194.2 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (45840177075607633428674 [0x9b50040229915a080c2] vs 1014663864233108701291 [0x37014a3099b7a0006b])
  UVM_INFO @ 6453194.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_rw_serr has 2 failures.

4.flash_ctrl_rw_serr.66982462952397941729932431880437319403654729764296397559933741345193866430412
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 10345111.0 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (52591689889807222210600 [0xb230050101086008028] vs 52591689889807356428328 [0xb23005010108e008028])
  UVM_INFO @ 10345111.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.flash_ctrl_rw_serr.54900008906559022158054384060032858705200199835716510590134948313307215945678
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 2100237.6 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (63245862294120694829184 [0xd6490a8199020005080] vs 63244709372616087982208 [0xd6480a8199020005080])
  UVM_INFO @ 2100237.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_rw_derr has 2 failures.

7.flash_ctrl_rw_derr.61808726349928256754889987934271401357057440872654968348151835252752377563361
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_rw_derr/latest/run.log

  UVM_ERROR @ 1488666.0 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (24838643354344887437312 [0x542816c020108104800] vs 24838643354344887568384 [0x542816c020108124800])
  UVM_INFO @ 1488666.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.flash_ctrl_rw_derr.260257348259145372078143031070299967416721091942521692752260445675212745763
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_rw_derr/latest/run.log

  UVM_ERROR @ 1797352.2 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (9232977626558282246 [0x8022203ba222ba06] vs 9521208002709961222 [0x8422203ba2223a06])
  UVM_INFO @ 1797352.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Error-[CNST-CIF] Constraints inconsistency failure has 3 failures:
- Test flash_ctrl_config_regwen has 3 failures.
  - 1.flash_ctrl_config_regwen.113658486763219240194832872708868340764993930156431331677180274619957622253159
    Line 328, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_config_regwen/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_flash_ctrl_env_0.1/seq_lib/flash_ctrl_config_regwen_vseq.sv, 46
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - 2.flash_ctrl_config_regwen.103496093698594850958700761716903904233851186439321579781743180148923119939493
    Line 328, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_config_regwen/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_flash_ctrl_env_0.1/seq_lib/flash_ctrl_config_regwen_vseq.sv, 46
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - ... and 1 more failures.

UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 3 failures:

Test flash_ctrl_rw_serr has 1 failures.

7.flash_ctrl_rw_serr.40392599597970029441800205191585186665587051775141411813963464339571766358773
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 706098.0 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 706098.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_ro has 2 failures.

11.flash_ctrl_ro.97384088248695283171754338240323509618228846369008384378047156263719761930966
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/11.flash_ctrl_ro/latest/run.log

  UVM_ERROR @ 9757.9 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 9757.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

13.flash_ctrl_ro.108479465732363790284533476369415240861335549136760913778326973636558616317073
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_ro/latest/run.log

  UVM_ERROR @ 1581084.2 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 1581084.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:289) m_otf_scb [process_read] unexpected double bit error * has 2 failures:
- Test flash_ctrl_read_word_sweep_derr has 2 failures.
  - 1.flash_ctrl_read_word_sweep_derr.69377648596835628397526284470145437980910125582778002725539504353764998617526
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_read_word_sweep_derr/latest/run.log
```
  UVM_ERROR @ 20131.1 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00004198
  UVM_INFO @ 20131.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.flash_ctrl_read_word_sweep_derr.28886203313746292008886536247606455342003525905356039532248747268500974754687
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_read_word_sweep_derr/latest/run.log
```
  UVM_ERROR @ 29672.9 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00016550
  UVM_INFO @ 29672.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_err triggered unexpectedly has 1 failures:
- Test flash_ctrl_phy_arb_redun has 1 failures.
  - 2.flash_ctrl_phy_arb_redun.65899850874476350113378774594553964989935917388893448619136899725842055836304
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_phy_arb_redun/latest/run.log
```
  UVM_ERROR @ 64164.2 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_err triggered unexpectedly
  UVM_INFO @ 64164.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_scoreboard.sv:481) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@1122277) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test flash_ctrl_oversize_error has 1 failures.

3.flash_ctrl_oversize_error.91285074088934117631441952721016928290254434496844875849970677673830232269132
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_oversize_error/latest/run.log

  UVM_ERROR @ 751981.6 ns: (cip_base_scoreboard.sv:481) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@1122277) { a_addr: 'h40110  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hd7  a_opcode: 'h4  a_user: 'h26a2a  d_param: 'h0  d_source: 'hd7  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h1  d_error: 'h1  d_sink: 'h0  d_user: 'heaa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 751981.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp c4686084_cb0d36f7:ffffffff_ffffffff mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 3.flash_ctrl_intr_rd.44651589946951500947520935257541495192541867813159158476651643970278731484714
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 1782265.1 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    4: obs:exp    c4686084_cb0d36f7:ffffffff_ffffffff  mismatch!!
  UVM_INFO @ 1782265.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 1 failures:
- Test flash_ctrl_wo has 1 failures.
  - 12.flash_ctrl_wo.47517764627421782533154687602724829946507714336480625421865664141472656093266
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_wo/latest/run.log
```
  Job ID: smart:cff0506a-89aa-48d4-a016-3350e480f112
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp e5c1281d_36fe63f6:ffffffff_36fe63f* mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 18.flash_ctrl_intr_rd.21902855386019510768130484391424940120697560966264287679984718341651416957713
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/18.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 1123915.5 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    0: obs:exp    e5c1281d_36fe63f6:ffffffff_36fe63f6  mismatch!!
  UVM_INFO @ 1123915.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *badab_7519c6be:ffffffff_7519c6be mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 34.flash_ctrl_intr_rd.47416708136885874253609793433963798679227473823217227429323793719424692569933
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/34.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 1830242.3 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    7: obs:exp    427badab_7519c6be:ffffffff_7519c6be  mismatch!!
  UVM_INFO @ 1830242.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```