01a208901a| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | flash_ctrl_smoke | 3.602m | 24.811us | 50 | 50 | 100.00 |
| V1 | smoke_hw | flash_ctrl_smoke_hw | 25.710s | 18.018us | 5 | 5 | 100.00 |
| V1 | csr_hw_reset | flash_ctrl_csr_hw_reset | 46.590s | 142.530us | 5 | 5 | 100.00 |
| V1 | csr_rw | flash_ctrl_csr_rw | 17.870s | 97.487us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | flash_ctrl_csr_bit_bash | 1.058m | 1.448ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | flash_ctrl_csr_aliasing | 1.103m | 2.601ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | flash_ctrl_csr_mem_rw_with_rand_reset | 19.890s | 46.776us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | flash_ctrl_csr_rw | 17.870s | 97.487us | 20 | 20 | 100.00 |
| flash_ctrl_csr_aliasing | 1.103m | 2.601ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | flash_ctrl_mem_walk | 13.510s | 24.168us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | flash_ctrl_mem_partial_access | 14.000s | 44.672us | 5 | 5 | 100.00 |
| V1 | TOTAL | 120 | 120 | 100.00 | |||
| V2 | sw_op | flash_ctrl_sw_op | 26.900s | 90.126us | 5 | 5 | 100.00 |
| V2 | host_read_direct | flash_ctrl_host_dir_rd | 1.914m | 251.394us | 5 | 5 | 100.00 |
| V2 | rma_hw_if | flash_ctrl_hw_rma | 36.956m | 375.990ms | 3 | 3 | 100.00 |
| flash_ctrl_hw_rma_reset | 20.776m | 380.268ms | 20 | 20 | 100.00 | ||
| flash_ctrl_lcmgr_intg | 13.900s | 15.976us | 20 | 20 | 100.00 | ||
| V2 | host_controller_arb | flash_ctrl_host_ctrl_arb | 49.308m | 285.404ms | 5 | 5 | 100.00 |
| V2 | erase_suspend | flash_ctrl_erase_suspend | 9.171m | 3.489ms | 5 | 5 | 100.00 |
| V2 | program_reset | flash_ctrl_prog_reset | 4.253m | 30.436ms | 28 | 30 | 93.33 |
| V2 | full_memory_access | flash_ctrl_full_mem_access | 1.255h | 97.828ms | 5 | 5 | 100.00 |
| V2 | rd_buff_eviction | flash_ctrl_rd_buff_evict | 3.322m | 1.388ms | 5 | 5 | 100.00 |
| V2 | rd_buff_eviction_w_ecc | flash_ctrl_rw_evict | 32.130s | 47.081us | 25 | 40 | 62.50 |
| flash_ctrl_rw_evict_all_en | 31.960s | 31.776us | 34 | 40 | 85.00 | ||
| flash_ctrl_re_evict | 39.380s | 116.128us | 20 | 20 | 100.00 | ||
| V2 | host_arb | flash_ctrl_phy_arb | 8.906m | 9.931ms | 20 | 20 | 100.00 |
| V2 | host_interleave | flash_ctrl_phy_arb | 8.906m | 9.931ms | 20 | 20 | 100.00 |
| V2 | memory_protection | flash_ctrl_mp_regions | 12.759m | 20.806ms | 20 | 20 | 100.00 |
| V2 | fetch_code | flash_ctrl_fetch_code | 30.780s | 4.862ms | 10 | 10 | 100.00 |
| V2 | all_partitions | flash_ctrl_rand_ops | 22.311m | 826.851us | 20 | 20 | 100.00 |
| V2 | error_mp | flash_ctrl_error_mp | 46.620m | 112.725ms | 10 | 10 | 100.00 |
| V2 | error_prog_win | flash_ctrl_error_prog_win | 18.795m | 794.449us | 10 | 10 | 100.00 |
| V2 | error_prog_type | flash_ctrl_error_prog_type | 52.689m | 584.615us | 5 | 5 | 100.00 |
| V2 | error_read_seed | flash_ctrl_hw_read_seed_err | 14.060s | 129.239us | 20 | 20 | 100.00 |
| V2 | read_write_overflow | flash_ctrl_oversize_error | 2.819m | 2.038ms | 5 | 5 | 100.00 |
| V2 | flash_ctrl_disable | flash_ctrl_disable | 22.780s | 12.628us | 50 | 50 | 100.00 |
| V2 | flash_ctrl_connect | flash_ctrl_connect | 16.290s | 40.398us | 80 | 80 | 100.00 |
| V2 | stress_all | flash_ctrl_stress_all | 36.976m | 970.763us | 5 | 5 | 100.00 |
| V2 | secret_partition | flash_ctrl_hw_sec_otp | 4.486m | 4.916ms | 50 | 50 | 100.00 |
| flash_ctrl_otp_reset | 2.252m | 135.795us | 80 | 80 | 100.00 | ||
| V2 | isolation_partition | flash_ctrl_hw_rma | 36.956m | 375.990ms | 3 | 3 | 100.00 |
| V2 | interrupts | flash_ctrl_intr_rd | 4.810m | 1.709ms | 37 | 40 | 92.50 |
| flash_ctrl_intr_wr | 1.326m | 2.578ms | 10 | 10 | 100.00 | ||
| flash_ctrl_intr_rd_slow_flash | 9.466m | 64.506ms | 40 | 40 | 100.00 | ||
| flash_ctrl_intr_wr_slow_flash | 4.290m | 78.134ms | 8 | 10 | 80.00 | ||
| V2 | invalid_op | flash_ctrl_invalid_op | 1.608m | 9.715ms | 20 | 20 | 100.00 |
| V2 | mid_op_rst | flash_ctrl_mid_op_rst | 1.369m | 11.881ms | 5 | 5 | 100.00 |
| V2 | double_bit_err | flash_ctrl_read_word_sweep_derr | 23.090s | 32.950us | 3 | 5 | 60.00 |
| flash_ctrl_ro_derr | 2.847m | 3.971ms | 10 | 10 | 100.00 | ||
| flash_ctrl_rw_derr | 12.204m | 5.051ms | 4 | 10 | 40.00 | ||
| flash_ctrl_derr_detect | 1.760m | 321.922us | 5 | 5 | 100.00 | ||
| flash_ctrl_integrity | 12.684m | 5.118ms | 3 | 5 | 60.00 | ||
| V2 | single_bit_err | flash_ctrl_read_word_sweep_serr | 22.870s | 24.733us | 4 | 5 | 80.00 |
| flash_ctrl_ro_serr | 2.679m | 613.975us | 10 | 10 | 100.00 | ||
| flash_ctrl_rw_serr | 10.603m | 17.605ms | 6 | 10 | 60.00 | ||
| V2 | singlebit_err_counter | flash_ctrl_serr_counter | 1.704m | 3.953ms | 5 | 5 | 100.00 |
| V2 | singlebit_err_address | flash_ctrl_serr_address | 1.561m | 4.148ms | 5 | 5 | 100.00 |
| V2 | scramble | flash_ctrl_wo | 4.097m | 2.909ms | 20 | 20 | 100.00 |
| flash_ctrl_write_word_sweep | 14.790s | 103.761us | 1 | 1 | 100.00 | ||
| flash_ctrl_read_word_sweep | 13.470s | 15.660us | 1 | 1 | 100.00 | ||
| flash_ctrl_ro | 2.359m | 526.825us | 20 | 20 | 100.00 | ||
| flash_ctrl_rw | 10.561m | 7.530ms | 18 | 20 | 90.00 | ||
| V2 | filesystem_support | flash_ctrl_fs_sup | 41.720s | 624.968us | 5 | 5 | 100.00 |
| V2 | rma_write_process_error | flash_ctrl_rma_err | 16.777m | 157.492ms | 3 | 3 | 100.00 |
| flash_ctrl_hw_prog_rma_wipe_err | 4.694m | 10.014ms | 20 | 20 | 100.00 | ||
| V2 | alert_test | flash_ctrl_alert_test | 14.510s | 75.447us | 50 | 50 | 100.00 |
| V2 | intr_test | flash_ctrl_intr_test | 14.150s | 52.113us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | flash_ctrl_tl_errors | 21.210s | 251.389us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | flash_ctrl_tl_errors | 21.210s | 251.389us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | flash_ctrl_csr_hw_reset | 46.590s | 142.530us | 5 | 5 | 100.00 |
| flash_ctrl_csr_rw | 17.870s | 97.487us | 20 | 20 | 100.00 | ||
| flash_ctrl_csr_aliasing | 1.103m | 2.601ms | 5 | 5 | 100.00 | ||
| flash_ctrl_same_csr_outstanding | 34.680s | 163.366us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | flash_ctrl_csr_hw_reset | 46.590s | 142.530us | 5 | 5 | 100.00 |
| flash_ctrl_csr_rw | 17.870s | 97.487us | 20 | 20 | 100.00 | ||
| flash_ctrl_csr_aliasing | 1.103m | 2.601ms | 5 | 5 | 100.00 | ||
| flash_ctrl_same_csr_outstanding | 34.680s | 163.366us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 968 | 1013 | 95.56 | |||
| V2S | shadow_reg_update_error | flash_ctrl_shadow_reg_errors | 16.290s | 14.618us | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | flash_ctrl_shadow_reg_errors | 16.290s | 14.618us | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | flash_ctrl_shadow_reg_errors | 16.290s | 14.618us | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | flash_ctrl_shadow_reg_errors | 16.290s | 14.618us | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | flash_ctrl_shadow_reg_errors_with_csr_rw | 16.520s | 11.992us | 20 | 20 | 100.00 |
| V2S | tl_intg_err | flash_ctrl_sec_cm | 1.376h | 25.711ms | 5 | 5 | 100.00 |
| flash_ctrl_tl_intg_err | 15.145m | 674.809us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_reg_bus_integrity | flash_ctrl_tl_intg_err | 15.145m | 674.809us | 20 | 20 | 100.00 |
| V2S | sec_cm_host_bus_integrity | flash_ctrl_tl_intg_err | 15.145m | 674.809us | 20 | 20 | 100.00 |
| V2S | sec_cm_mem_bus_integrity | flash_ctrl_rd_intg | 31.970s | 65.060us | 3 | 3 | 100.00 |
| flash_ctrl_wr_intg | 15.280s | 46.129us | 3 | 3 | 100.00 | ||
| V2S | sec_cm_scramble_key_sideload | flash_ctrl_smoke | 3.602m | 24.811us | 50 | 50 | 100.00 |
| V2S | sec_cm_lc_ctrl_intersig_mubi | flash_ctrl_otp_reset | 2.252m | 135.795us | 80 | 80 | 100.00 |
| flash_ctrl_disable | 22.780s | 12.628us | 50 | 50 | 100.00 | ||
| flash_ctrl_sec_info_access | 1.535m | 8.965ms | 50 | 50 | 100.00 | ||
| flash_ctrl_connect | 16.290s | 40.398us | 80 | 80 | 100.00 | ||
| V2S | sec_cm_ctrl_config_regwen | flash_ctrl_config_regwen | 13.860s | 19.151us | 2 | 5 | 40.00 |
| V2S | sec_cm_data_regions_config_regwen | flash_ctrl_csr_rw | 17.870s | 97.487us | 20 | 20 | 100.00 |
| V2S | sec_cm_data_regions_config_shadow | flash_ctrl_shadow_reg_errors | 16.290s | 14.618us | 20 | 20 | 100.00 |
| V2S | sec_cm_info_regions_config_regwen | flash_ctrl_csr_rw | 17.870s | 97.487us | 20 | 20 | 100.00 |
| V2S | sec_cm_info_regions_config_shadow | flash_ctrl_shadow_reg_errors | 16.290s | 14.618us | 20 | 20 | 100.00 |
| V2S | sec_cm_bank_config_regwen | flash_ctrl_csr_rw | 17.870s | 97.487us | 20 | 20 | 100.00 |
| V2S | sec_cm_bank_config_shadow | flash_ctrl_shadow_reg_errors | 16.290s | 14.618us | 20 | 20 | 100.00 |
| V2S | sec_cm_mem_ctrl_global_esc | flash_ctrl_disable | 22.780s | 12.628us | 50 | 50 | 100.00 |
| V2S | sec_cm_mem_ctrl_local_esc | flash_ctrl_rd_intg | 31.970s | 65.060us | 3 | 3 | 100.00 |
| flash_ctrl_access_after_disable | 13.930s | 34.890us | 3 | 3 | 100.00 | ||
| V2S | sec_cm_mem_disable_config_mubi | flash_ctrl_disable | 22.780s | 12.628us | 50 | 50 | 100.00 |
| V2S | sec_cm_exec_config_redun | flash_ctrl_fetch_code | 30.780s | 4.862ms | 10 | 10 | 100.00 |
| V2S | sec_cm_mem_scramble | flash_ctrl_rw | 10.561m | 7.530ms | 18 | 20 | 90.00 |
| V2S | sec_cm_mem_integrity | flash_ctrl_rw_serr | 10.603m | 17.605ms | 6 | 10 | 60.00 |
| flash_ctrl_rw_derr | 12.204m | 5.051ms | 4 | 10 | 40.00 | ||
| flash_ctrl_integrity | 12.684m | 5.118ms | 3 | 5 | 60.00 | ||
| V2S | sec_cm_rma_entry_mem_sec_wipe | flash_ctrl_hw_rma | 36.956m | 375.990ms | 3 | 3 | 100.00 |
| V2S | sec_cm_ctrl_fsm_sparse | flash_ctrl_sec_cm | 1.376h | 25.711ms | 5 | 5 | 100.00 |
| V2S | sec_cm_phy_fsm_sparse | flash_ctrl_sec_cm | 1.376h | 25.711ms | 5 | 5 | 100.00 |
| V2S | sec_cm_phy_prog_fsm_sparse | flash_ctrl_sec_cm | 1.376h | 25.711ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ctr_redun | flash_ctrl_sec_cm | 1.376h | 25.711ms | 5 | 5 | 100.00 |
| V2S | sec_cm_phy_arbiter_ctrl_redun | flash_ctrl_phy_arb_redun | 24.790s | 636.061us | 4 | 5 | 80.00 |
| V2S | sec_cm_phy_host_grant_ctrl_consistency | flash_ctrl_phy_host_grant_err | 14.390s | 57.788us | 5 | 5 | 100.00 |
| V2S | sec_cm_phy_ack_ctrl_consistency | flash_ctrl_phy_ack_consistency | 23.650s | 1.325ms | 5 | 5 | 100.00 |
| V2S | sec_cm_fifo_ctr_redun | flash_ctrl_sec_cm | 1.376h | 25.711ms | 5 | 5 | 100.00 |
| V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | flash_ctrl_sec_cm | 1.376h | 25.711ms | 5 | 5 | 100.00 |
| V2S | sec_cm_prog_tl_lc_gate_fsm_sparse | flash_ctrl_sec_cm | 1.376h | 25.711ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 140 | 144 | 97.22 | |||
| V3 | asymmetric_read_path | flash_ctrl_rd_ooo | 45.380s | 72.375us | 1 | 1 | 100.00 |
| V3 | stress_all_with_rand_reset | flash_ctrl_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 1 | 1 | 100.00 | |||
| TOTAL | 1229 | 1278 | 96.17 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 9 | 9 | 9 | 100.00 |
| V2 | 55 | 55 | 44 | 80.00 |
| V2S | 12 | 12 | 10 | 83.33 |
| V3 | 2 | 1 | 1 | 50.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 96.41 | 95.84 | 94.13 | 98.85 | 91.84 | 98.27 | 98.01 | 97.90 |
UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 19 failures:
0.flash_ctrl_rw_evict.37236807679652876092508802559586097514389645303870152345505825425778687501481
Line 291, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_evict/latest/run.log
UVM_FATAL @ 36387.2 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x0005c010
UVM_INFO @ 36387.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.flash_ctrl_rw_evict.87065233344536842642418803935582246262970992428215469612881810061673486384885
Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rw_evict/latest/run.log
UVM_FATAL @ 39993.0 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x0009aab8
UVM_INFO @ 39993.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 12 more failures.
7.flash_ctrl_rw_evict_all_en.31850348539466939021188624689571900409666103889990274596240760712051278671400
Line 290, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_rw_evict_all_en/latest/run.log
UVM_FATAL @ 25330.3 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x000823c0
UVM_INFO @ 25330.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.flash_ctrl_rw_evict_all_en.65493320429765552324484499550379316189868082852479684342641233882526940780728
Line 291, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_rw_evict_all_en/latest/run.log
UVM_FATAL @ 9724.3 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00049f00
UVM_INFO @ 9724.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:289) m_otf_scb [process_read] unexpected double bit error * has 6 failures:
Test flash_ctrl_read_word_sweep_derr has 2 failures.
0.flash_ctrl_read_word_sweep_derr.66809794764407216291986071185049022915847478848214845777871894858323725287459
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_read_word_sweep_derr/latest/run.log
UVM_ERROR @ 9950.5 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00015670
UVM_INFO @ 9950.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.flash_ctrl_read_word_sweep_derr.13571171138172506092943461089225212979214950514447469696613331118786773789095
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_read_word_sweep_derr/latest/run.log
UVM_ERROR @ 5694.0 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00000120
UVM_INFO @ 5694.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test flash_ctrl_integrity has 2 failures.
1.flash_ctrl_integrity.27856069781032765901809365723494055419190318076928461141214914676632030101616
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_integrity/latest/run.log
UVM_ERROR @ 8472756.2 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00003e00
UVM_INFO @ 8472756.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.flash_ctrl_integrity.91908293215008384614134116726442593304046202323636179024750804860467042106472
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_integrity/latest/run.log
UVM_ERROR @ 458023.8 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00003200
UVM_INFO @ 458023.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test flash_ctrl_rw_derr has 2 failures.
4.flash_ctrl_rw_derr.4211031923779890465854896133605789192040891696565619639833299974681774519384
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw_derr/latest/run.log
UVM_ERROR @ 1224412.4 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00002218
UVM_INFO @ 1224412.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.flash_ctrl_rw_derr.80323978286351522451001050801449743311283933218029806948457745732346251898165
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_rw_derr/latest/run.log
UVM_ERROR @ 4590119.9 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00003c00
UVM_INFO @ 4590119.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 5 failures:
Test flash_ctrl_rw_serr has 2 failures.
0.flash_ctrl_rw_serr.74690760003007654913669978560040292599403031629334685555003145272549144609337
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_serr/latest/run.log
UVM_ERROR @ 633322.8 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (7536666448664295243891 [0x1989041fc17081a0073] vs 2814299965794650030195 [0x989041fc17081a0073])
UVM_INFO @ 633322.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.flash_ctrl_rw_serr.5680627844668053697049889045606531881390277179154511835365685967236819507916
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_rw_serr/latest/run.log
UVM_ERROR @ 5613777.5 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (4003524714496971251840 [0xd90811044081242080] vs 4003524714496954474624 [0xd90811044080242080])
UVM_INFO @ 5613777.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test flash_ctrl_rw_derr has 3 failures.
1.flash_ctrl_rw_derr.114272344143972451057614795576787595581280483509032963078386881741091521672895
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_derr/latest/run.log
UVM_ERROR @ 5002446.1 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (37779587232085717033025 [0x800091856c0084c2041] vs 37779588357985623875649 [0x800091c56c0084c2041])
UVM_INFO @ 5002446.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.flash_ctrl_rw_derr.6396926247757465764233767540514619929740331790316143087793288699121602429324
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_rw_derr/latest/run.log
UVM_ERROR @ 5808800.3 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (309352295798221063460 [0x10c520220280884524] vs 309352295798222112036 [0x10c520220280984524])
UVM_INFO @ 5808800.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 5 failures:
Test flash_ctrl_intr_wr_slow_flash has 2 failures.
0.flash_ctrl_intr_wr_slow_flash.62321256750603550967822290677442823477103250374725173020005846607094587625787
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_intr_wr_slow_flash/latest/run.log
Job ID: smart:b640cc10-187e-4a1d-9631-551715b851b0
3.flash_ctrl_intr_wr_slow_flash.20777674275650597501567654716519601437330921582823814544544980875934956549152
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_intr_wr_slow_flash/latest/run.log
Job ID: smart:9350a4c4-e020-4c0a-abf0-e6712be5e7f2
Test flash_ctrl_prog_reset has 2 failures.
4.flash_ctrl_prog_reset.14242504199870252784266964494521968757571568746537200220231962550272823883635
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_prog_reset/latest/run.log
Job ID: smart:f689982e-12ff-4f19-9a12-05d254a86fbe
25.flash_ctrl_prog_reset.58418072408302818843873121443615952997577997708920063538034457710573697143939
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/25.flash_ctrl_prog_reset/latest/run.log
Job ID: smart:c5d381ff-819e-4643-936d-fe29fa90c3d5
Test flash_ctrl_rw has 1 failures.
5.flash_ctrl_rw.5605013486196362008985871577052487017279170035758468276072395263682543646903
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_rw/latest/run.log
Job ID: smart:7898fae4-dec6-4619-aa0f-0a5762d455f4
Error-[CNST-CIF] Constraints inconsistency failure has 3 failures:
0.flash_ctrl_config_regwen.98193388332382076043026042183810600649638539629797969110597864837046375052396
Line 328, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_config_regwen/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_flash_ctrl_env_0.1/seq_lib/flash_ctrl_config_regwen_vseq.sv, 46
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
1.flash_ctrl_config_regwen.89487942046737275113497908507560213210127002372319583654476235033729348663252
Line 328, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_config_regwen/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_flash_ctrl_env_0.1/seq_lib/flash_ctrl_config_regwen_vseq.sv, 46
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
... and 1 more failures.
UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 3 failures:
Test flash_ctrl_rw has 1 failures.
6.flash_ctrl_rw.44273088046587642734866072118149579528337495749597315574881262282928271891694
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_rw/latest/run.log
UVM_ERROR @ 1678446.7 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
UVM_INFO @ 1678446.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test flash_ctrl_rw_serr has 2 failures.
6.flash_ctrl_rw_serr.42070359731673278142927562911981485197330308544307088823583158254469514658062
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_rw_serr/latest/run.log
UVM_ERROR @ 5426818.5 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
UVM_INFO @ 5426818.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.flash_ctrl_rw_serr.105405810362477345399404755578594473395242724529739102939272949896598836955559
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_rw_serr/latest/run.log
UVM_ERROR @ 13122427.6 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
UVM_INFO @ 13122427.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_err triggered unexpectedly has 2 failures:
Test flash_ctrl_read_word_sweep_serr has 1 failures.
3.flash_ctrl_read_word_sweep_serr.39903164580266297796553678763244965560976854375741268950699177803199524553084
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_read_word_sweep_serr/latest/run.log
UVM_ERROR @ 10310.3 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_err triggered unexpectedly
UVM_INFO @ 10310.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test flash_ctrl_phy_arb_redun has 1 failures.
3.flash_ctrl_phy_arb_redun.114844619310516472015557219163203972714763035414829213820879028838241529839696
Line 286, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_phy_arb_redun/latest/run.log
UVM_ERROR @ 20764.9 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_err triggered unexpectedly
UVM_INFO @ 20764.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 2 failures:
Test flash_ctrl_rw_evict has 1 failures.
12.flash_ctrl_rw_evict.77028104632236120580199458809450996597881868920291139339578816758330906290050
Line 287, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_rw_evict/latest/run.log
UVM_ERROR @ 19913.3 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
UVM_INFO @ 19913.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test flash_ctrl_rw_evict_all_en has 1 failures.
30.flash_ctrl_rw_evict_all_en.88826399934805907288730480204509358317441926117237206919065392767265170358956
Line 287, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/30.flash_ctrl_rw_evict_all_en/latest/run.log
UVM_ERROR @ 9033.1 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
UVM_INFO @ 9033.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *afcd_bba105b4:ffffffff_bba105b* mismatch!! has 1 failures:
2.flash_ctrl_intr_rd.56471758190798425926968347036289691722133037441808345870119586073498974483815
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_intr_rd/latest/run.log
UVM_ERROR @ 1089899.2 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] 7: obs:exp 7843afcd_bba105b4:ffffffff_bba105b4 mismatch!!
UVM_INFO @ 1089899.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 1 failures:
6.flash_ctrl_rw_derr.31482400668962047533415041025234287795751603137517288507257984587172612668514
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_rw_derr/latest/run.log
UVM_ERROR @ 4210119.7 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (2732568925536065726467 [0x94220300012008a803] vs 40511500788493227436035 [0x894220300012008a803])
UVM_INFO @ 4210119.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp b2077824_90e3cab9:ffffffff_ffffffff mismatch!! has 1 failures:
13.flash_ctrl_intr_rd.94998046655630000783628971521359981003648600719297319281838606372069881511065
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_intr_rd/latest/run.log
UVM_ERROR @ 2644916.7 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] 2: obs:exp b2077824_90e3cab9:ffffffff_ffffffff mismatch!!
UVM_INFO @ 2644916.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp d5f16255_44de3782:ffffffff_44de* mismatch!! has 1 failures:
15.flash_ctrl_intr_rd.98786923896016825803185282384421683701033515066796267546643220389712992220509
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/15.flash_ctrl_intr_rd/latest/run.log
UVM_ERROR @ 1439456.7 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] 0: obs:exp d5f16255_44de3782:ffffffff_44de3782 mismatch!!
UVM_INFO @ 1439456.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---