a182fcef27| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | flash_ctrl_smoke | 3.883m | 1.479ms | 50 | 50 | 100.00 |
| V1 | smoke_hw | flash_ctrl_smoke_hw | 25.820s | 26.515us | 5 | 5 | 100.00 |
| V1 | csr_hw_reset | flash_ctrl_csr_hw_reset | 45.440s | 28.088us | 5 | 5 | 100.00 |
| V1 | csr_rw | flash_ctrl_csr_rw | 18.330s | 101.316us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | flash_ctrl_csr_bit_bash | 1.531m | 23.902ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | flash_ctrl_csr_aliasing | 39.690s | 1.310ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | flash_ctrl_csr_mem_rw_with_rand_reset | 19.830s | 497.493us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | flash_ctrl_csr_rw | 18.330s | 101.316us | 20 | 20 | 100.00 |
| flash_ctrl_csr_aliasing | 39.690s | 1.310ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | flash_ctrl_mem_walk | 13.540s | 48.744us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | flash_ctrl_mem_partial_access | 13.630s | 29.948us | 5 | 5 | 100.00 |
| V1 | TOTAL | 120 | 120 | 100.00 | |||
| V2 | sw_op | flash_ctrl_sw_op | 27.230s | 20.282us | 5 | 5 | 100.00 |
| V2 | host_read_direct | flash_ctrl_host_dir_rd | 1.704m | 115.182us | 5 | 5 | 100.00 |
| V2 | rma_hw_if | flash_ctrl_hw_rma | 33.204m | 105.871ms | 3 | 3 | 100.00 |
| flash_ctrl_hw_rma_reset | 18.340m | 350.297ms | 20 | 20 | 100.00 | ||
| flash_ctrl_lcmgr_intg | 13.970s | 33.871us | 19 | 20 | 95.00 | ||
| V2 | host_controller_arb | flash_ctrl_host_ctrl_arb | 40.090m | 434.758ms | 5 | 5 | 100.00 |
| V2 | erase_suspend | flash_ctrl_erase_suspend | 10.270m | 9.506ms | 5 | 5 | 100.00 |
| V2 | program_reset | flash_ctrl_prog_reset | 4.416m | 12.115ms | 30 | 30 | 100.00 |
| V2 | full_memory_access | flash_ctrl_full_mem_access | 1.243h | 84.131ms | 5 | 5 | 100.00 |
| V2 | rd_buff_eviction | flash_ctrl_rd_buff_evict | 2.631m | 2.912ms | 5 | 5 | 100.00 |
| V2 | rd_buff_eviction_w_ecc | flash_ctrl_rw_evict | 32.660s | 82.456us | 26 | 40 | 65.00 |
| flash_ctrl_rw_evict_all_en | 32.890s | 52.885us | 36 | 40 | 90.00 | ||
| flash_ctrl_re_evict | 38.350s | 225.717us | 20 | 20 | 100.00 | ||
| V2 | host_arb | flash_ctrl_phy_arb | 9.428m | 1.445ms | 20 | 20 | 100.00 |
| V2 | host_interleave | flash_ctrl_phy_arb | 9.428m | 1.445ms | 20 | 20 | 100.00 |
| V2 | memory_protection | flash_ctrl_mp_regions | 15.699m | 14.769ms | 20 | 20 | 100.00 |
| V2 | fetch_code | flash_ctrl_fetch_code | 27.290s | 178.673us | 10 | 10 | 100.00 |
| V2 | all_partitions | flash_ctrl_rand_ops | 22.613m | 1.696ms | 20 | 20 | 100.00 |
| V2 | error_mp | flash_ctrl_error_mp | 44.503m | 25.345ms | 9 | 10 | 90.00 |
| V2 | error_prog_win | flash_ctrl_error_prog_win | 18.509m | 1.005ms | 10 | 10 | 100.00 |
| V2 | error_prog_type | flash_ctrl_error_prog_type | 47.784m | 5.016ms | 5 | 5 | 100.00 |
| V2 | error_read_seed | flash_ctrl_hw_read_seed_err | 14.030s | 22.841us | 20 | 20 | 100.00 |
| V2 | read_write_overflow | flash_ctrl_oversize_error | 3.577m | 1.901ms | 4 | 5 | 80.00 |
| V2 | flash_ctrl_disable | flash_ctrl_disable | 23.000s | 27.086us | 50 | 50 | 100.00 |
| V2 | flash_ctrl_connect | flash_ctrl_connect | 16.430s | 49.589us | 80 | 80 | 100.00 |
| V2 | stress_all | flash_ctrl_stress_all | 25.397m | 337.042us | 5 | 5 | 100.00 |
| V2 | secret_partition | flash_ctrl_hw_sec_otp | 4.579m | 12.997ms | 50 | 50 | 100.00 |
| flash_ctrl_otp_reset | 2.278m | 39.627us | 80 | 80 | 100.00 | ||
| V2 | isolation_partition | flash_ctrl_hw_rma | 33.204m | 105.871ms | 3 | 3 | 100.00 |
| V2 | interrupts | flash_ctrl_intr_rd | 5.436m | 3.324ms | 37 | 40 | 92.50 |
| flash_ctrl_intr_wr | 1.471m | 2.891ms | 10 | 10 | 100.00 | ||
| flash_ctrl_intr_rd_slow_flash | 6.790m | 47.626ms | 40 | 40 | 100.00 | ||
| flash_ctrl_intr_wr_slow_flash | 6.239m | 252.094ms | 10 | 10 | 100.00 | ||
| V2 | invalid_op | flash_ctrl_invalid_op | 1.568m | 8.908ms | 20 | 20 | 100.00 |
| V2 | mid_op_rst | flash_ctrl_mid_op_rst | 1.421m | 8.048ms | 5 | 5 | 100.00 |
| V2 | double_bit_err | flash_ctrl_read_word_sweep_derr | 22.510s | 28.928us | 4 | 5 | 80.00 |
| flash_ctrl_ro_derr | 2.838m | 2.570ms | 10 | 10 | 100.00 | ||
| flash_ctrl_rw_derr | 13.702m | 16.116ms | 6 | 10 | 60.00 | ||
| flash_ctrl_derr_detect | 1.821m | 221.761us | 5 | 5 | 100.00 | ||
| flash_ctrl_integrity | 11.937m | 13.388ms | 4 | 5 | 80.00 | ||
| V2 | single_bit_err | flash_ctrl_read_word_sweep_serr | 22.670s | 93.937us | 2 | 5 | 40.00 |
| flash_ctrl_ro_serr | 2.932m | 1.242ms | 10 | 10 | 100.00 | ||
| flash_ctrl_rw_serr | 13.506m | 62.667ms | 8 | 10 | 80.00 | ||
| V2 | singlebit_err_counter | flash_ctrl_serr_counter | 1.629m | 1.663ms | 5 | 5 | 100.00 |
| V2 | singlebit_err_address | flash_ctrl_serr_address | 1.742m | 7.127ms | 5 | 5 | 100.00 |
| V2 | scramble | flash_ctrl_wo | 4.116m | 5.087ms | 20 | 20 | 100.00 |
| flash_ctrl_write_word_sweep | 15.000s | 40.768us | 1 | 1 | 100.00 | ||
| flash_ctrl_read_word_sweep | 13.220s | 26.363us | 1 | 1 | 100.00 | ||
| flash_ctrl_ro | 2.467m | 1.794ms | 18 | 20 | 90.00 | ||
| flash_ctrl_rw | 12.460m | 10.557ms | 19 | 20 | 95.00 | ||
| V2 | filesystem_support | flash_ctrl_fs_sup | 45.740s | 6.405ms | 4 | 5 | 80.00 |
| V2 | rma_write_process_error | flash_ctrl_rma_err | 17.575m | 303.041ms | 3 | 3 | 100.00 |
| flash_ctrl_hw_prog_rma_wipe_err | 5.013m | 10.013ms | 20 | 20 | 100.00 | ||
| V2 | alert_test | flash_ctrl_alert_test | 14.430s | 111.295us | 50 | 50 | 100.00 |
| V2 | intr_test | flash_ctrl_intr_test | 13.960s | 15.161us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | flash_ctrl_tl_errors | 21.120s | 603.269us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | flash_ctrl_tl_errors | 21.120s | 603.269us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | flash_ctrl_csr_hw_reset | 45.440s | 28.088us | 5 | 5 | 100.00 |
| flash_ctrl_csr_rw | 18.330s | 101.316us | 20 | 20 | 100.00 | ||
| flash_ctrl_csr_aliasing | 39.690s | 1.310ms | 5 | 5 | 100.00 | ||
| flash_ctrl_same_csr_outstanding | 35.410s | 900.113us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | flash_ctrl_csr_hw_reset | 45.440s | 28.088us | 5 | 5 | 100.00 |
| flash_ctrl_csr_rw | 18.330s | 101.316us | 20 | 20 | 100.00 | ||
| flash_ctrl_csr_aliasing | 39.690s | 1.310ms | 5 | 5 | 100.00 | ||
| flash_ctrl_same_csr_outstanding | 35.410s | 900.113us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 974 | 1013 | 96.15 | |||
| V2S | shadow_reg_update_error | flash_ctrl_shadow_reg_errors | 15.980s | 23.245us | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | flash_ctrl_shadow_reg_errors | 15.980s | 23.245us | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | flash_ctrl_shadow_reg_errors | 15.980s | 23.245us | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | flash_ctrl_shadow_reg_errors | 15.980s | 23.245us | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | flash_ctrl_shadow_reg_errors_with_csr_rw | 15.900s | 13.641us | 20 | 20 | 100.00 |
| V2S | tl_intg_err | flash_ctrl_sec_cm | 1.371h | 3.813ms | 5 | 5 | 100.00 |
| flash_ctrl_tl_intg_err | 15.124m | 1.340ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_reg_bus_integrity | flash_ctrl_tl_intg_err | 15.124m | 1.340ms | 20 | 20 | 100.00 |
| V2S | sec_cm_host_bus_integrity | flash_ctrl_tl_intg_err | 15.124m | 1.340ms | 20 | 20 | 100.00 |
| V2S | sec_cm_mem_bus_integrity | flash_ctrl_rd_intg | 31.490s | 116.475us | 3 | 3 | 100.00 |
| flash_ctrl_wr_intg | 15.470s | 309.466us | 3 | 3 | 100.00 | ||
| V2S | sec_cm_scramble_key_sideload | flash_ctrl_smoke | 3.883m | 1.479ms | 50 | 50 | 100.00 |
| V2S | sec_cm_lc_ctrl_intersig_mubi | flash_ctrl_otp_reset | 2.278m | 39.627us | 80 | 80 | 100.00 |
| flash_ctrl_disable | 23.000s | 27.086us | 50 | 50 | 100.00 | ||
| flash_ctrl_sec_info_access | 1.590m | 20.033ms | 50 | 50 | 100.00 | ||
| flash_ctrl_connect | 16.430s | 49.589us | 80 | 80 | 100.00 | ||
| V2S | sec_cm_ctrl_config_regwen | flash_ctrl_config_regwen | 14.070s | 41.162us | 3 | 5 | 60.00 |
| V2S | sec_cm_data_regions_config_regwen | flash_ctrl_csr_rw | 18.330s | 101.316us | 20 | 20 | 100.00 |
| V2S | sec_cm_data_regions_config_shadow | flash_ctrl_shadow_reg_errors | 15.980s | 23.245us | 20 | 20 | 100.00 |
| V2S | sec_cm_info_regions_config_regwen | flash_ctrl_csr_rw | 18.330s | 101.316us | 20 | 20 | 100.00 |
| V2S | sec_cm_info_regions_config_shadow | flash_ctrl_shadow_reg_errors | 15.980s | 23.245us | 20 | 20 | 100.00 |
| V2S | sec_cm_bank_config_regwen | flash_ctrl_csr_rw | 18.330s | 101.316us | 20 | 20 | 100.00 |
| V2S | sec_cm_bank_config_shadow | flash_ctrl_shadow_reg_errors | 15.980s | 23.245us | 20 | 20 | 100.00 |
| V2S | sec_cm_mem_ctrl_global_esc | flash_ctrl_disable | 23.000s | 27.086us | 50 | 50 | 100.00 |
| V2S | sec_cm_mem_ctrl_local_esc | flash_ctrl_rd_intg | 31.490s | 116.475us | 3 | 3 | 100.00 |
| flash_ctrl_access_after_disable | 13.930s | 39.538us | 3 | 3 | 100.00 | ||
| V2S | sec_cm_mem_disable_config_mubi | flash_ctrl_disable | 23.000s | 27.086us | 50 | 50 | 100.00 |
| V2S | sec_cm_exec_config_redun | flash_ctrl_fetch_code | 27.290s | 178.673us | 10 | 10 | 100.00 |
| V2S | sec_cm_mem_scramble | flash_ctrl_rw | 12.460m | 10.557ms | 19 | 20 | 95.00 |
| V2S | sec_cm_mem_integrity | flash_ctrl_rw_serr | 13.506m | 62.667ms | 8 | 10 | 80.00 |
| flash_ctrl_rw_derr | 13.702m | 16.116ms | 6 | 10 | 60.00 | ||
| flash_ctrl_integrity | 11.937m | 13.388ms | 4 | 5 | 80.00 | ||
| V2S | sec_cm_rma_entry_mem_sec_wipe | flash_ctrl_hw_rma | 33.204m | 105.871ms | 3 | 3 | 100.00 |
| V2S | sec_cm_ctrl_fsm_sparse | flash_ctrl_sec_cm | 1.371h | 3.813ms | 5 | 5 | 100.00 |
| V2S | sec_cm_phy_fsm_sparse | flash_ctrl_sec_cm | 1.371h | 3.813ms | 5 | 5 | 100.00 |
| V2S | sec_cm_phy_prog_fsm_sparse | flash_ctrl_sec_cm | 1.371h | 3.813ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ctr_redun | flash_ctrl_sec_cm | 1.371h | 3.813ms | 5 | 5 | 100.00 |
| V2S | sec_cm_phy_arbiter_ctrl_redun | flash_ctrl_phy_arb_redun | 23.510s | 756.471us | 5 | 5 | 100.00 |
| V2S | sec_cm_phy_host_grant_ctrl_consistency | flash_ctrl_phy_host_grant_err | 14.150s | 47.849us | 5 | 5 | 100.00 |
| V2S | sec_cm_phy_ack_ctrl_consistency | flash_ctrl_phy_ack_consistency | 14.430s | 228.598us | 5 | 5 | 100.00 |
| V2S | sec_cm_fifo_ctr_redun | flash_ctrl_sec_cm | 1.371h | 3.813ms | 5 | 5 | 100.00 |
| V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | flash_ctrl_sec_cm | 1.371h | 3.813ms | 5 | 5 | 100.00 |
| V2S | sec_cm_prog_tl_lc_gate_fsm_sparse | flash_ctrl_sec_cm | 1.371h | 3.813ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 142 | 144 | 98.61 | |||
| V3 | asymmetric_read_path | flash_ctrl_rd_ooo | 44.430s | 116.179us | 1 | 1 | 100.00 |
| V3 | stress_all_with_rand_reset | flash_ctrl_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 1 | 1 | 100.00 | |||
| TOTAL | 1237 | 1278 | 96.79 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 9 | 9 | 9 | 100.00 |
| V2 | 55 | 55 | 41 | 74.55 |
| V2S | 12 | 12 | 11 | 91.67 |
| V3 | 2 | 1 | 1 | 50.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 96.54 | 95.84 | 94.19 | 98.85 | 92.52 | 98.24 | 98.11 | 98.00 |
UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 17 failures:
1.flash_ctrl_rw_evict.12706561366426598120569504301251019344771128420364174997749442645662812009684
Line 292, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_evict/latest/run.log
UVM_FATAL @ 43299.5 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x000006a8
UVM_INFO @ 43299.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.flash_ctrl_rw_evict.97804613270845846291511982938623228324413006587724363485583239687926672004113
Line 299, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rw_evict/latest/run.log
UVM_FATAL @ 319738.0 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x000000f0
UVM_INFO @ 319738.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 12 more failures.
2.flash_ctrl_rw_evict_all_en.109841507356266787842049596785007412683797443670099321636613129214189449884270
Line 294, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rw_evict_all_en/latest/run.log
UVM_FATAL @ 57845.6 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00000060
UVM_INFO @ 57845.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.flash_ctrl_rw_evict_all_en.61263579231057605466097840276887814459850317278763363695591502624656357850347
Line 288, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/15.flash_ctrl_rw_evict_all_en/latest/run.log
UVM_FATAL @ 10840.9 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x000672f0
UVM_INFO @ 10840.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_err triggered unexpectedly has 5 failures:
1.flash_ctrl_read_word_sweep_serr.68727113267054813956165425679815788731358467866212169130689793933978273801551
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_read_word_sweep_serr/latest/run.log
UVM_ERROR @ 8597.8 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_err triggered unexpectedly
UVM_INFO @ 8597.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.flash_ctrl_read_word_sweep_serr.21365777694222419788408473973557779809101620475076768332654461104481621797667
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_read_word_sweep_serr/latest/run.log
UVM_ERROR @ 14739.3 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_err triggered unexpectedly
UVM_INFO @ 14739.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
14.flash_ctrl_ro.50573294494775267945130180751895309467950789546715079386567523288114652267624
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/14.flash_ctrl_ro/latest/run.log
UVM_ERROR @ 9076.6 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_err triggered unexpectedly
UVM_INFO @ 9076.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.flash_ctrl_ro.99941777550042060618443423415667063477937211850141973999113930558492449462860
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/17.flash_ctrl_ro/latest/run.log
UVM_ERROR @ 49380.7 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_err triggered unexpectedly
UVM_INFO @ 49380.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 4 failures:
Test flash_ctrl_oversize_error has 1 failures.
0.flash_ctrl_oversize_error.4800299695631588018240201593108285137211896603818942766275986538667620382573
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_oversize_error/latest/run.log
Job ID: smart:4112ca09-f74c-456b-b8ac-5dbfa5bdc12f
Test flash_ctrl_rw_serr has 1 failures.
5.flash_ctrl_rw_serr.67519190591190433214470417255005149549363477849806888485107374093912301025043
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_rw_serr/latest/run.log
Job ID: smart:9d34450d-d212-4219-ae12-01fd62a19b14
Test flash_ctrl_rw_derr has 1 failures.
7.flash_ctrl_rw_derr.33923475890140785690047716800286287641360657154661488210664652345669541469638
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_rw_derr/latest/run.log
Job ID: smart:c6459ed1-f61d-44b4-9fda-5a0afe8c6dfa
Test flash_ctrl_rw has 1 failures.
18.flash_ctrl_rw.42672659405360500867213237959947229475259449592913021825280868082830873680660
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/18.flash_ctrl_rw/latest/run.log
Job ID: smart:98a19ef8-41dd-4575-a207-b75346a15843
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:289) m_otf_scb [process_read] unexpected double bit error * has 3 failures:
Test flash_ctrl_integrity has 1 failures.
1.flash_ctrl_integrity.49536899440234362864425736075831571485893081251996499837115727714327554892435
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_integrity/latest/run.log
UVM_ERROR @ 2026802.6 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00002800
UVM_INFO @ 2026802.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test flash_ctrl_read_word_sweep_derr has 1 failures.
3.flash_ctrl_read_word_sweep_derr.75486733305510226643809024671340125434987074285723656129701282262548038350794
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_read_word_sweep_derr/latest/run.log
UVM_ERROR @ 23991.9 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x0001c0a8
UVM_INFO @ 23991.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test flash_ctrl_rw_derr has 1 failures.
9.flash_ctrl_rw_derr.103013584684677605406321608108030808897526632577751658649833786979640499976930
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_rw_derr/latest/run.log
UVM_ERROR @ 1549538.1 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00003400
UVM_INFO @ 1549538.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 2 failures:
1.flash_ctrl_rw_derr.14097621191600573320535647951653846162834998852649365253679243753352249023875
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_derr/latest/run.log
UVM_ERROR @ 1354916.3 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (9596234058649961627790 [0x20836800150a802008e] vs 9596243065849216368782 [0x20836a00150a802008e])
UVM_INFO @ 1354916.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.flash_ctrl_rw_derr.58539892243995330625643300576064242142212690898975841126881291209405769860348
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_rw_derr/latest/run.log
UVM_ERROR @ 11770444.4 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (7396317897094238311360 [0x190f487c409164413c0] vs 7387094525057383535552 [0x1907487c409164413c0])
UVM_INFO @ 11770444.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[CNST-CIF] Constraints inconsistency failure has 2 failures:
1.flash_ctrl_config_regwen.73392155676459298442163509644195959532987949341235473717858573094634978575572
Line 328, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_config_regwen/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_flash_ctrl_env_0.1/seq_lib/flash_ctrl_config_regwen_vseq.sv, 46
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
3.flash_ctrl_config_regwen.51780729631673425807748513813771647506798346599522960711862623841092243151959
Line 328, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_config_regwen/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_flash_ctrl_env_0.1/seq_lib/flash_ctrl_config_regwen_vseq.sv, 46
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
UVM_ERROR (mem_bkdr_util.sv:197) [mem_bkdr_util[FlashPartInfo][*]] addr * is out of bounds: size = * has 1 failures:
0.flash_ctrl_fs_sup.105014136462276266871524182317524493846815435313075593953881773115957134093477
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_fs_sup/latest/run.log
UVM_ERROR @ 214906.6 ns: (mem_bkdr_util.sv:197) [mem_bkdr_util[FlashPartInfo][0]] addr 5000 is out of bounds: size = 5000
UVM_INFO @ 214906.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_env_cfg.sv:705) [cfg] Check failed data[i] === exp_data[i] (* [*] vs * [*]) has 1 failures:
6.flash_ctrl_error_mp.41820588503415337503804046587787884930313776584798209126105786938442685410684
Line 588, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_error_mp/latest/run.log
UVM_ERROR @ 216791.2 ns: (flash_ctrl_env_cfg.sv:705) [cfg] Check failed data[i] === exp_data[i] (0x4b195f32 [1001011000110010101111100110010] vs 0x4faff45d [1001111101011111111010001011101])
UVM_INFO @ 216791.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 1 failures:
6.flash_ctrl_rw_evict_all_en.2400207052100580723752886238651642008440765394426021335506840626638754346962
Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_rw_evict_all_en/latest/run.log
UVM_ERROR @ 11151.7 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
UVM_INFO @ 11151.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 1 failures:
7.flash_ctrl_rw_serr.17709393884098527212576976918344612982284097721154823617325263523137811587353
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_rw_serr/latest/run.log
UVM_ERROR @ 4755562.5 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
UVM_INFO @ 4755562.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.std_fault_status.lcmgr_intg_err reset value: * has 1 failures:
15.flash_ctrl_lcmgr_intg.26146663162937414702632965219305298699845333530912755815529655315582385251179
Line 285, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/15.flash_ctrl_lcmgr_intg/latest/run.log
UVM_ERROR @ 26177.5 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.std_fault_status.lcmgr_intg_err reset value: 0x0
UVM_INFO @ 26177.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *b21a47e_3c3cad79:ffffffff_3c3cad* mismatch!! has 1 failures:
26.flash_ctrl_intr_rd.33469243315492914155443954628689952221664542743155782428695318203103043716244
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/26.flash_ctrl_intr_rd/latest/run.log
UVM_ERROR @ 2318986.8 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] 4: obs:exp 8b21a47e_3c3cad79:ffffffff_3c3cad79 mismatch!!
UVM_INFO @ 2318986.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *f6bd_126fd1bc:ffffffff_126fd1bc mismatch!! has 1 failures:
27.flash_ctrl_intr_rd.16625435361992151850149751380119065575579105617909103005988731769100579043758
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/27.flash_ctrl_intr_rd/latest/run.log
UVM_ERROR @ 4802050.2 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] 3: obs:exp 3342f6bd_126fd1bc:ffffffff_126fd1bc mismatch!!
UVM_INFO @ 4802050.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp fad88200_ab9b9c31:ffffffff_ffffffff mismatch!! has 1 failures:
34.flash_ctrl_intr_rd.5183031658024573371369416051247519984942031832826331965545840797876358249392
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/34.flash_ctrl_intr_rd/latest/run.log
UVM_ERROR @ 461895.3 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] 1: obs:exp fad88200_ab9b9c31:ffffffff_ffffffff mismatch!!
UVM_INFO @ 461895.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---