FLASH_CTRL Simulation Results

Wednesday June 05 2024 22:14:46 UTC

GitHub Revision: `b29ffbb03c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 104714960319679935410420483500971829136303708457300037460974663680452494898918

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.652m	936.116us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	27.050s	52.400us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	45.580s	27.114us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	18.180s	1.149ms	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.274m	9.511ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	58.480s	1.907ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	19.700s	238.011us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	18.180s	1.149ms	20	20	100.00
		flash_ctrl_csr_aliasing	58.480s	1.907ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	14.000s	51.911us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.670s	112.705us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.720s	68.313us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	1.670m	59.558us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	42.186m	1.024s	3	3	100.00
		flash_ctrl_hw_rma_reset	20.324m	630.480ms	20	20	100.00
		flash_ctrl_lcmgr_intg	14.170s	26.331us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	48.507m	315.912ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	9.485m	13.938ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	3.702m	2.858ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.119h	212.278ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.303m	5.515ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	32.140s	57.256us	27	40	67.50
		flash_ctrl_rw_evict_all_en	32.240s	29.111us	39	40	97.50
		flash_ctrl_re_evict	39.420s	421.859us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	9.142m	6.300ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	9.142m	6.300ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	12.292m	40.008ms	19	20	95.00
V2	fetch_code	flash_ctrl_fetch_code	32.300s	2.435ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	24.033m	3.674ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	42.377m	19.981ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	16.540m	714.861us	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	46.674m	2.205ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	14.040s	15.676us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.390m	2.669ms	4	5	80.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.560s	17.869us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.270s	73.359us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	19.201m	1.127ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.666m	6.569ms	50	50	100.00
		flash_ctrl_otp_reset	2.312m	365.870us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	42.186m	1.024s	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	4.907m	1.725ms	37	40	92.50
		flash_ctrl_intr_wr	1.300m	10.036ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	8.231m	42.582ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	9.746m	453.897ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.502m	972.253us	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.221m	13.664ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	22.530s	19.142us	3	5	60.00
		flash_ctrl_ro_derr	3.019m	3.095ms	10	10	100.00
		flash_ctrl_rw_derr	13.250m	72.827ms	7	10	70.00
		flash_ctrl_derr_detect	1.744m	123.647us	5	5	100.00
		flash_ctrl_integrity	12.713m	37.374ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	22.310s	28.445us	3	5	60.00
		flash_ctrl_ro_serr	2.380m	2.890ms	10	10	100.00
		flash_ctrl_rw_serr	12.168m	34.406ms	9	10	90.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.782m	3.101ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.337m	2.109ms	5	5	100.00
V2	scramble	flash_ctrl_wo	4.004m	2.868ms	20	20	100.00
		flash_ctrl_write_word_sweep	15.550s	62.135us	1	1	100.00
		flash_ctrl_read_word_sweep	13.450s	36.682us	1	1	100.00
		flash_ctrl_ro	2.241m	4.882ms	20	20	100.00
		flash_ctrl_rw	10.235m	8.274ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	42.970s	386.988us	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	15.043m	40.201ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.426m	10.012ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.500s	277.399us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.150s	34.069us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	20.110s	61.352us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	20.110s	61.352us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	45.580s	27.114us	5	5	100.00
		flash_ctrl_csr_rw	18.180s	1.149ms	20	20	100.00
		flash_ctrl_csr_aliasing	58.480s	1.907ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.250s	953.565us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	45.580s	27.114us	5	5	100.00
		flash_ctrl_csr_rw	18.180s	1.149ms	20	20	100.00
		flash_ctrl_csr_aliasing	58.480s	1.907ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.250s	953.565us	20	20	100.00
V2		TOTAL			986	1013	97.33
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.110s	15.831us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.110s	15.831us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.110s	15.831us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.110s	15.831us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.180s	13.048us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.330h	5.684ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.299m	1.336ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.299m	1.336ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.299m	1.336ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	32.100s	996.438us	3	3	100.00
		flash_ctrl_wr_intg	15.080s	86.490us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.652m	936.116us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.312m	365.870us	80	80	100.00
		flash_ctrl_disable	22.560s	17.869us	50	50	100.00
		flash_ctrl_sec_info_access	1.438m	2.540ms	50	50	100.00
		flash_ctrl_connect	16.270s	73.359us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	13.910s	40.395us	2	5	40.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	18.180s	1.149ms	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.110s	15.831us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	18.180s	1.149ms	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.110s	15.831us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	18.180s	1.149ms	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.110s	15.831us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.560s	17.869us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	32.100s	996.438us	3	3	100.00
		flash_ctrl_access_after_disable	14.010s	15.229us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.560s	17.869us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	32.300s	2.435ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	10.235m	8.274ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	12.168m	34.406ms	9	10	90.00
		flash_ctrl_rw_derr	13.250m	72.827ms	7	10	70.00
		flash_ctrl_integrity	12.713m	37.374ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	42.186m	1.024s	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.330h	5.684ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.330h	5.684ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.330h	5.684ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.330h	5.684ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	23.810s	756.057us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	13.970s	56.047us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	15.880s	387.451us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.330h	5.684ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.330h	5.684ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.330h	5.684ms	5	5	100.00
V2S		TOTAL			141	144	97.92
V3	asymmetric_read_path	flash_ctrl_rd_ooo	45.990s	153.584us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1248	1278	97.65

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	46	83.64
V2S	12	12	11	91.67
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.52	95.84	94.24	98.85	92.52	98.24	98.01	97.93

Failure Buckets

UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 14 failures:

Test flash_ctrl_rw_evict has 13 failures.

0.flash_ctrl_rw_evict.28626900724049841452695522054418591095979633136656576761179445868624643664806
Line 291, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_evict/latest/run.log

  UVM_FATAL @ 159901.8 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00080298
  UVM_INFO @ 159901.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.flash_ctrl_rw_evict.61365436196051248514013715400268328016770357316373602796400193581554838091889
Line 291, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_rw_evict/latest/run.log

  UVM_FATAL @ 22139.9 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x000029a0
  UVM_INFO @ 22139.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 11 more failures.

Test flash_ctrl_rw_evict_all_en has 1 failures.

17.flash_ctrl_rw_evict_all_en.69163947109180482310437063999409743063084419546420437426931133012326893986473
Line 292, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/17.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_FATAL @ 104986.5 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00001780
  UVM_INFO @ 104986.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Error-[CNST-CIF] Constraints inconsistency failure has 3 failures:
- Test flash_ctrl_config_regwen has 3 failures.
  - 0.flash_ctrl_config_regwen.112360819265132545195642947578905382894609590497587780759147282926206183256076
    Line 328, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_config_regwen/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_flash_ctrl_env_0.1/seq_lib/flash_ctrl_config_regwen_vseq.sv, 46
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - 1.flash_ctrl_config_regwen.59374959270588871177725781050152129466896358393097805215948841948297692929713
    Line 328, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_config_regwen/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_flash_ctrl_env_0.1/seq_lib/flash_ctrl_config_regwen_vseq.sv, 46
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - ... and 1 more failures.
UVM_ERROR (flash_otf_item.sv:247) [rd_scr] ecc error is detected has 2 failures:
- Test flash_ctrl_read_word_sweep_serr has 1 failures.
  - 0.flash_ctrl_read_word_sweep_serr.100866821055634759839383043518455978038131439201030051366112494953749297702566
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_read_word_sweep_serr/latest/run.log
```
  UVM_ERROR @ 5474.1 ns: (flash_otf_item.sv:247) [rd_scr] ecc error is detected
  UVM_INFO @ 5474.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_oversize_error has 1 failures.
  - 2.flash_ctrl_oversize_error.38298334479902088344668790833994466168324461590458220025784278614054394924526
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_oversize_error/latest/run.log
```
  UVM_ERROR @ 2094020.6 ns: (flash_otf_item.sv:247) [rd_scr] ecc error is detected
  UVM_INFO @ 2094020.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 2 failures:

Test flash_ctrl_rw_serr has 1 failures.

3.flash_ctrl_rw_serr.44650843361112625238269312442316999969680260000140189697110613512852868798863
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 3755107.3 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (37786871711961771835432 [0x8006e30029a42068028] vs 37786871712099210788904 [0x8006e3002ba42068028])
  UVM_INFO @ 3755107.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_rw_derr has 1 failures.

4.flash_ctrl_rw_derr.103280244710758317846584537502966254791275881511319151239844416871347074428726
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw_derr/latest/run.log

  UVM_ERROR @ 7259131.6 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (673597076824944301120 [0x2484098c8084505440] vs 673597076842124170304 [0x2484098c8484505440])
  UVM_INFO @ 7259131.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:289) m_otf_scb [process_read] unexpected double bit error * has 2 failures:
- Test flash_ctrl_read_word_sweep_derr has 2 failures.
  - 3.flash_ctrl_read_word_sweep_derr.97401408665634588106665648081433645011507680506260655607144969768147988547923
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_read_word_sweep_derr/latest/run.log
```
  UVM_ERROR @ 8598.9 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x0001ced0
  UVM_INFO @ 8598.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.flash_ctrl_read_word_sweep_derr.27584863260981965983499462617430635391387657250779933361765865249033733385835
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_read_word_sweep_derr/latest/run.log
```
  UVM_ERROR @ 5166.7 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x000020c0
  UVM_INFO @ 5166.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 2 failures:
- Test flash_ctrl_rw_derr has 2 failures.
  - 6.flash_ctrl_rw_derr.23461446330437408264339481552386980755979824307988119569403923239000242534558
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_rw_derr/latest/run.log
```
  Job ID: smart:fe2b4464-4ccf-4496-a484-10442054e268
```
  - 9.flash_ctrl_rw_derr.18725227840510133751836977497350148625900816978521152197866785871004837365064
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_rw_derr/latest/run.log
```
  Job ID: smart:630fe6d4-249b-44b4-81b1-f3b61f0841fc
```
UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 1 failures:
- Test flash_ctrl_read_word_sweep_serr has 1 failures.
  - 2.flash_ctrl_read_word_sweep_serr.58832112792842285250628822522733994382157316964581436315256824199261527233943
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_read_word_sweep_serr/latest/run.log
```
  UVM_ERROR @ 19459.7 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 19459.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (flash_ctrl_mp_regions_vseq.sv:196) [flash_ctrl_mp_regions_vseq] wait timeout for alert_count == exp_alertcnt after do_mp_reg() alert_cnt:* exp_alert_cnt:* has 1 failures:
- Test flash_ctrl_mp_regions has 1 failures.
  - 4.flash_ctrl_mp_regions.104478099613481573027788945148576292395708641960257436737134104120812358282790
    Line 1025, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_mp_regions/latest/run.log
```
  UVM_FATAL @ 415331.8 ns: (flash_ctrl_mp_regions_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.flash_ctrl_mp_regions_vseq] wait timeout for alert_count == exp_alertcnt after do_mp_reg() alert_cnt:36  exp_alert_cnt:37
  UVM_INFO @ 415331.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp a750b6ab_2dd4f7ba:ffffffff_ffffffff mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 6.flash_ctrl_intr_rd.107149967759499007090707476097538318583721524806442171017048412179557899591841
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 1614120.3 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    1: obs:exp    a750b6ab_2dd4f7ba:ffffffff_ffffffff  mismatch!!
  UVM_INFO @ 1614120.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *_cf6d5e75:ffffffff_cf6d5e* mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 9.flash_ctrl_intr_rd.78433483481349779897148703949839836942376492201383855020179217827494608519679
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 1727902.8 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    4: obs:exp    47023372_cf6d5e75:ffffffff_cf6d5e75  mismatch!!
  UVM_INFO @ 1727902.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *fe7d981_3c6dc6cf:ffffffff_ffffffff mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 23.flash_ctrl_intr_rd.51864774723532034394567216083153933280330070005920891136849782724363133389074
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/23.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 1284789.8 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    5: obs:exp    4fe7d981_3c6dc6cf:ffffffff_ffffffff  mismatch!!
  UVM_INFO @ 1284789.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```