FLASH_CTRL Simulation Results

Thursday June 06 2024 19:04:47 UTC

GitHub Revision: `32d52b8d41`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 59908589074363629542901507660786833114562191729708937078847065421241135561861

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.776m	95.335us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	27.190s	14.058us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	45.860s	47.687us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.610s	154.502us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.340m	6.085ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.141m	1.843ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	19.310s	609.889us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.610s	154.502us	20	20	100.00
		flash_ctrl_csr_aliasing	1.141m	1.843ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.760s	54.464us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.810s	239.420us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	27.570s	22.967us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	1.698m	56.889us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	37.153m	543.572ms	3	3	100.00
		flash_ctrl_hw_rma_reset	17.538m	260.234ms	20	20	100.00
		flash_ctrl_lcmgr_intg	14.060s	15.932us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	46.862m	275.943ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	9.053m	4.491ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	4.151m	17.518ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.168h	99.781ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.135m	1.444ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	32.680s	52.221us	29	40	72.50
		flash_ctrl_rw_evict_all_en	32.100s	32.585us	36	40	90.00
		flash_ctrl_re_evict	39.130s	215.632us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	9.556m	5.564ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	9.556m	5.564ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	11.239m	59.349ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	27.760s	1.243ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	20.751m	11.955ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	43.508m	13.145ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	16.751m	2.154ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	57.444m	3.241ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	13.940s	15.320us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.945m	7.466ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.750s	12.680us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.760s	14.944us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	24.855m	3.536ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.382m	12.978ms	50	50	100.00
		flash_ctrl_otp_reset	2.292m	276.774us	79	80	98.75
V2	isolation_partition	flash_ctrl_hw_rma	37.153m	543.572ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	4.604m	1.698ms	36	40	90.00
		flash_ctrl_intr_wr	1.389m	5.699ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	9.304m	25.713ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	6.444m	343.127ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.652m	4.021ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.351m	12.786ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	23.190s	27.129us	3	5	60.00
		flash_ctrl_ro_derr	2.715m	581.612us	10	10	100.00
		flash_ctrl_rw_derr	12.683m	4.744ms	8	10	80.00
		flash_ctrl_derr_detect	1.843m	327.189us	5	5	100.00
		flash_ctrl_integrity	12.352m	17.276ms	4	5	80.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	23.080s	363.716us	3	5	60.00
		flash_ctrl_ro_serr	2.784m	4.013ms	10	10	100.00
		flash_ctrl_rw_serr	11.670m	4.207ms	6	10	60.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.860m	12.072ms	4	5	80.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.451m	773.534us	5	5	100.00
V2	scramble	flash_ctrl_wo	3.750m	13.609ms	20	20	100.00
		flash_ctrl_write_word_sweep	15.460s	39.775us	1	1	100.00
		flash_ctrl_read_word_sweep	13.900s	56.882us	1	1	100.00
		flash_ctrl_ro	2.468m	6.131ms	20	20	100.00
		flash_ctrl_rw	11.298m	8.169ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	41.060s	804.228us	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	20.041m	251.737ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.624m	10.012ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	15.110s	236.789us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.250s	24.384us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	21.220s	133.856us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	21.220s	133.856us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	45.860s	47.687us	5	5	100.00
		flash_ctrl_csr_rw	17.610s	154.502us	20	20	100.00
		flash_ctrl_csr_aliasing	1.141m	1.843ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.900s	1.372ms	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	45.860s	47.687us	5	5	100.00
		flash_ctrl_csr_rw	17.610s	154.502us	20	20	100.00
		flash_ctrl_csr_aliasing	1.141m	1.843ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.900s	1.372ms	20	20	100.00
V2		TOTAL			981	1013	96.84
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.370s	24.955us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.370s	24.955us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.370s	24.955us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.370s	24.955us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.010s	165.861us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.736h	11.294ms	1	5	20.00
		flash_ctrl_tl_intg_err	15.264m	767.038us	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.264m	767.038us	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.264m	767.038us	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	32.890s	64.231us	3	3	100.00
		flash_ctrl_wr_intg	15.510s	167.061us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.776m	95.335us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.292m	276.774us	79	80	98.75
		flash_ctrl_disable	22.750s	12.680us	50	50	100.00
		flash_ctrl_sec_info_access	1.607m	2.278ms	50	50	100.00
		flash_ctrl_connect	16.760s	14.944us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.290s	20.304us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.610s	154.502us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.370s	24.955us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.610s	154.502us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.370s	24.955us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.610s	154.502us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.370s	24.955us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.750s	12.680us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	32.890s	64.231us	3	3	100.00
		flash_ctrl_access_after_disable	14.190s	22.656us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.750s	12.680us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	27.760s	1.243ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	11.298m	8.169ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	11.670m	4.207ms	6	10	60.00
		flash_ctrl_rw_derr	12.683m	4.744ms	8	10	80.00
		flash_ctrl_integrity	12.352m	17.276ms	4	5	80.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	37.153m	543.572ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.736h	11.294ms	1	5	20.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.736h	11.294ms	1	5	20.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.736h	11.294ms	1	5	20.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.736h	11.294ms	1	5	20.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	22.860s	907.111us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.280s	46.068us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.370s	15.564us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.736h	11.294ms	1	5	20.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.736h	11.294ms	1	5	20.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.736h	11.294ms	1	5	20.00
V2S		TOTAL			140	144	97.22
V3	asymmetric_read_path	flash_ctrl_rd_ooo	43.900s	78.241us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1242	1278	97.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	45	81.82
V2S	12	12	11	91.67
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.27	95.67	94.12	97.54	92.52	98.08	98.03	97.97

Failure Buckets

UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 15 failures:

Test flash_ctrl_rw_evict has 11 failures.

5.flash_ctrl_rw_evict.10518969996328741019539068672024783852605936090033732430683155291932278231604
Line 295, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_rw_evict/latest/run.log

  UVM_FATAL @ 12368.4 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x000800b8
  UVM_INFO @ 12368.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.flash_ctrl_rw_evict.54023124107724857474921800177046681794637618543710395121529764878231308665287
Line 291, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_rw_evict/latest/run.log

  UVM_FATAL @ 34069.3 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00002790
  UVM_INFO @ 34069.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 9 more failures.

Test flash_ctrl_rw_evict_all_en has 4 failures.

5.flash_ctrl_rw_evict_all_en.112949145149084188127004439318938082356892486117910694494070047768586826124835
Line 292, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_FATAL @ 27099.3 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x0000c1d0
  UVM_INFO @ 27099.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

15.flash_ctrl_rw_evict_all_en.26919262558749525693030657400726004535018433949873936477825541020409782182406
Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/15.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_FATAL @ 13834.7 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x000623b0
  UVM_INFO @ 13834.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 5 failures:

Test flash_ctrl_rw_derr has 2 failures.

1.flash_ctrl_rw_derr.70435980927398112668019182054726556749312719037395705153074834711180310001179
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_derr/latest/run.log

  UVM_ERROR @ 6486366.1 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (49151426603161411994624 [0xa688111a02800a14400] vs 49151426603161411996672 [0xa688111a02800a14c00])
  UVM_INFO @ 6486366.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.flash_ctrl_rw_derr.27518792812330710120784738898225187772325939366626925126587715348822602861977
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_rw_derr/latest/run.log

  UVM_ERROR @ 1181087.0 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (16011854533814430795276 [0x364011ea0102501060c] vs 16011854533813893924364 [0x364011ea0100501060c])
  UVM_INFO @ 1181087.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_integrity has 1 failures.

4.flash_ctrl_integrity.27859626542233235879008530339527872430262375174684372057235093841785495383578
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_integrity/latest/run.log

  UVM_ERROR @ 1512095.7 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (3127452867223078862880 [0xa98a2094c8b0848020] vs 2363721059410218067201 [0x8023382400b00c2501])
  UVM_INFO @ 1512095.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_rw_serr has 2 failures.

8.flash_ctrl_rw_serr.103980229809441378319423139917815054175788629213220915957973226424064959420330
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 2462889.6 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (30769367681975968924184 [0x68402c173a90a150218] vs 30769367681993148793368 [0x68402c173ad0a150218])
  UVM_INFO @ 2462889.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.flash_ctrl_rw_serr.57311863728757769851880654562996306708043353349019235318885735632626496782394
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 1258196.3 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (23925427353950276569314 [0x51100010812244c48e2] vs 23925427356149299824866 [0x51100010a12244c48e2])
  UVM_INFO @ 1258196.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Offending '(!$isunknown(rdata_o))' has 2 failures:
- Test flash_ctrl_sec_cm has 2 failures.
  - 0.flash_ctrl_sec_cm.95371310433761044651252717410842725921494136551854017530220216991067785269517
    Line 601, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_sec_cm/latest/run.log
```
      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @ 207000.2 ns: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @ 207000.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 4.flash_ctrl_sec_cm.87435853670567783194659536186823580329020932371076521521911991616839000953895
    Line 526, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_sec_cm/latest/run.log
```
      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @ 22565.0 ns: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @ 22565.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:289) m_otf_scb [process_read] unexpected double bit error * has 2 failures:
- Test flash_ctrl_read_word_sweep_derr has 2 failures.
  - 1.flash_ctrl_read_word_sweep_derr.97211377097116489851349062123318875058259577567787446116481833041681743983054
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_read_word_sweep_derr/latest/run.log
```
  UVM_ERROR @ 9820.0 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00001058
  UVM_INFO @ 9820.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.flash_ctrl_read_word_sweep_derr.3121789999037209313298890109923792019261582147888920724221480495516936561919
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_read_word_sweep_derr/latest/run.log
```
  UVM_ERROR @ 21485.8 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00001060
  UVM_INFO @ 21485.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$isunknown(mem_tl_o.d_valid))' has 2 failures:
- Test flash_ctrl_sec_cm has 2 failures.
  - 1.flash_ctrl_sec_cm.86656520130372272127733612364421037325713098744221024774588426946464522756820
    Line 311, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_sec_cm/latest/run.log
```
      Offending '(!$isunknown(mem_tl_o.d_valid))'
  UVM_ERROR @ 63451.1 ns: (flash_ctrl.sv:1376) [ASSERT FAILED] MemTlDValidKnownO_A
  UVM_INFO @ 63451.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 2.flash_ctrl_sec_cm.32210955605517839758305996907961542950363744035196386288111345879468398497080
    Line 434, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_sec_cm/latest/run.log
```
      Offending '(!$isunknown(mem_tl_o.d_valid))'
  UVM_ERROR @ 247725.5 ns: (flash_ctrl.sv:1376) [ASSERT FAILED] MemTlDValidKnownO_A
  UVM_INFO @ 247725.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_err triggered unexpectedly has 2 failures:
- Test flash_ctrl_read_word_sweep_serr has 2 failures.
  - 3.flash_ctrl_read_word_sweep_serr.20958843740283958668127727878427647269443157225361074156001153157099990603027
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_read_word_sweep_serr/latest/run.log
```
  UVM_ERROR @ 5384.4 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_err triggered unexpectedly
  UVM_INFO @ 5384.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.flash_ctrl_read_word_sweep_serr.7747651328876732482599980270219540011332912452367644746887526407328954910597
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_read_word_sweep_serr/latest/run.log
```
  UVM_ERROR @ 19875.7 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_err triggered unexpectedly
  UVM_INFO @ 19875.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 2 failures:
- Test flash_ctrl_rw_serr has 2 failures.
  - 3.flash_ctrl_rw_serr.15586034052110980060551792461080922923562989383758386186322825438980732054242
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_rw_serr/latest/run.log
```
  UVM_ERROR @ 1333564.0 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 1333564.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.flash_ctrl_rw_serr.60456090018563149570099925028553461745792672657340075886427891513656554381880
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_rw_serr/latest/run.log
```
  UVM_ERROR @ 6953885.3 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 6953885.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp b5ddbae1_d33f43b2:ffffffff_ffffffff mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 1.flash_ctrl_intr_rd.86066871203021048528296691973114391538322009953287845294028757869745488780067
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 3003084.1 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    3: obs:exp    b5ddbae1_d33f43b2:ffffffff_ffffffff  mismatch!!
  UVM_INFO @ 3003084.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 1 failures:
- Test flash_ctrl_serr_counter has 1 failures.
  - 2.flash_ctrl_serr_counter.77834134533341052920291193066682291434658750106185844185906250946072216315539
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_serr_counter/latest/run.log
```
  Job ID: smart:19aa361e-e365-42dd-890a-eb7696fa7e6c
```
Offending 'dst_req_o' has 1 failures:
- Test flash_ctrl_otp_reset has 1 failures.
  - 12.flash_ctrl_otp_reset.100484501469502267631172635754677952827818625297952965899190700391436350431655
    Line 354, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_otp_reset/latest/run.log
```
      Offending 'dst_req_o'
  UVM_ERROR @ 33883.0 ns: (prim_sync_reqack.sv:354) [ASSERT FAILED] SyncReqAckAckNeedsReq
  UVM_INFO @ 33883.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *e9ac5_9cc0bf0e:ffffffff_9cc0bf0e mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 15.flash_ctrl_intr_rd.79559780026577807084791582548233833908092663294088829699251385312655121703473
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/15.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 4063188.0 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    2: obs:exp    390e9ac5_9cc0bf0e:ffffffff_9cc0bf0e  mismatch!!
  UVM_INFO @ 4063188.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *f264_4292fadb:ffffffff_ffffffff mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 30.flash_ctrl_intr_rd.12922190775876466039738692983625007555994511389397742087294838562963109782533
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/30.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 5046646.5 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    4: obs:exp    7159f264_4292fadb:ffffffff_ffffffff  mismatch!!
  UVM_INFO @ 5046646.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *ff71bb_a8b3280a:ffffffff_ffffffff mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 32.flash_ctrl_intr_rd.95077512590544511135175672841104935864663004834258039585333520287881306656009
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/32.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 559052.0 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    5: obs:exp    47ff71bb_a8b3280a:ffffffff_ffffffff  mismatch!!
  UVM_INFO @ 559052.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```