302b24f3c6| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | flash_ctrl_smoke | 3.589m | 33.824us | 50 | 50 | 100.00 |
| V1 | smoke_hw | flash_ctrl_smoke_hw | 26.610s | 44.147us | 5 | 5 | 100.00 |
| V1 | csr_hw_reset | flash_ctrl_csr_hw_reset | 46.350s | 104.003us | 5 | 5 | 100.00 |
| V1 | csr_rw | flash_ctrl_csr_rw | 17.670s | 55.333us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | flash_ctrl_csr_bit_bash | 1.204m | 2.772ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | flash_ctrl_csr_aliasing | 1.118m | 9.324ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | flash_ctrl_csr_mem_rw_with_rand_reset | 21.500s | 108.042us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | flash_ctrl_csr_rw | 17.670s | 55.333us | 20 | 20 | 100.00 |
| flash_ctrl_csr_aliasing | 1.118m | 9.324ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | flash_ctrl_mem_walk | 13.480s | 15.429us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | flash_ctrl_mem_partial_access | 13.810s | 20.436us | 5 | 5 | 100.00 |
| V1 | TOTAL | 120 | 120 | 100.00 | |||
| V2 | sw_op | flash_ctrl_sw_op | 26.920s | 24.796us | 5 | 5 | 100.00 |
| V2 | host_read_direct | flash_ctrl_host_dir_rd | 2.079m | 67.200us | 5 | 5 | 100.00 |
| V2 | rma_hw_if | flash_ctrl_hw_rma | 34.183m | 169.004ms | 3 | 3 | 100.00 |
| flash_ctrl_hw_rma_reset | 17.368m | 160.189ms | 20 | 20 | 100.00 | ||
| flash_ctrl_lcmgr_intg | 13.980s | 26.485us | 20 | 20 | 100.00 | ||
| V2 | host_controller_arb | flash_ctrl_host_ctrl_arb | 41.551m | 371.346ms | 5 | 5 | 100.00 |
| V2 | erase_suspend | flash_ctrl_erase_suspend | 9.383m | 37.261ms | 5 | 5 | 100.00 |
| V2 | program_reset | flash_ctrl_prog_reset | 4.013m | 9.629ms | 30 | 30 | 100.00 |
| V2 | full_memory_access | flash_ctrl_full_mem_access | 1.258h | 489.110ms | 5 | 5 | 100.00 |
| V2 | rd_buff_eviction | flash_ctrl_rd_buff_evict | 2.501m | 1.434ms | 5 | 5 | 100.00 |
| V2 | rd_buff_eviction_w_ecc | flash_ctrl_rw_evict | 31.750s | 93.940us | 33 | 40 | 82.50 |
| flash_ctrl_rw_evict_all_en | 32.690s | 44.176us | 37 | 40 | 92.50 | ||
| flash_ctrl_re_evict | 39.020s | 131.689us | 20 | 20 | 100.00 | ||
| V2 | host_arb | flash_ctrl_phy_arb | 11.188m | 5.514ms | 20 | 20 | 100.00 |
| V2 | host_interleave | flash_ctrl_phy_arb | 11.188m | 5.514ms | 20 | 20 | 100.00 |
| V2 | memory_protection | flash_ctrl_mp_regions | 17.942m | 53.131ms | 20 | 20 | 100.00 |
| V2 | fetch_code | flash_ctrl_fetch_code | 27.200s | 469.290us | 10 | 10 | 100.00 |
| V2 | all_partitions | flash_ctrl_rand_ops | 22.376m | 6.196ms | 20 | 20 | 100.00 |
| V2 | error_mp | flash_ctrl_error_mp | 40.654m | 6.483ms | 10 | 10 | 100.00 |
| V2 | error_prog_win | flash_ctrl_error_prog_win | 15.075m | 745.831us | 10 | 10 | 100.00 |
| V2 | error_prog_type | flash_ctrl_error_prog_type | 47.469m | 1.654ms | 5 | 5 | 100.00 |
| V2 | error_read_seed | flash_ctrl_hw_read_seed_err | 13.830s | 25.990us | 20 | 20 | 100.00 |
| V2 | read_write_overflow | flash_ctrl_oversize_error | 3.353m | 1.153ms | 5 | 5 | 100.00 |
| V2 | flash_ctrl_disable | flash_ctrl_disable | 22.550s | 119.234us | 50 | 50 | 100.00 |
| V2 | flash_ctrl_connect | flash_ctrl_connect | 16.540s | 15.231us | 80 | 80 | 100.00 |
| V2 | stress_all | flash_ctrl_stress_all | 30.062m | 17.126ms | 5 | 5 | 100.00 |
| V2 | secret_partition | flash_ctrl_hw_sec_otp | 4.326m | 9.143ms | 50 | 50 | 100.00 |
| flash_ctrl_otp_reset | 2.291m | 70.905us | 80 | 80 | 100.00 | ||
| V2 | isolation_partition | flash_ctrl_hw_rma | 34.183m | 169.004ms | 3 | 3 | 100.00 |
| V2 | interrupts | flash_ctrl_intr_rd | 4.120m | 27.462ms | 37 | 40 | 92.50 |
| flash_ctrl_intr_wr | 1.361m | 2.939ms | 10 | 10 | 100.00 | ||
| flash_ctrl_intr_rd_slow_flash | 5.915m | 32.877ms | 40 | 40 | 100.00 | ||
| flash_ctrl_intr_wr_slow_flash | 3.846m | 73.684ms | 10 | 10 | 100.00 | ||
| V2 | invalid_op | flash_ctrl_invalid_op | 1.534m | 2.046ms | 20 | 20 | 100.00 |
| V2 | mid_op_rst | flash_ctrl_mid_op_rst | 1.244m | 11.709ms | 5 | 5 | 100.00 |
| V2 | double_bit_err | flash_ctrl_read_word_sweep_derr | 22.740s | 19.222us | 2 | 5 | 40.00 |
| flash_ctrl_ro_derr | 2.931m | 629.730us | 10 | 10 | 100.00 | ||
| flash_ctrl_rw_derr | 12.732m | 4.596ms | 7 | 10 | 70.00 | ||
| flash_ctrl_derr_detect | 1.782m | 124.858us | 5 | 5 | 100.00 | ||
| flash_ctrl_integrity | 12.497m | 9.569ms | 3 | 5 | 60.00 | ||
| V2 | single_bit_err | flash_ctrl_read_word_sweep_serr | 22.780s | 22.895us | 4 | 5 | 80.00 |
| flash_ctrl_ro_serr | 2.534m | 900.486us | 10 | 10 | 100.00 | ||
| flash_ctrl_rw_serr | 11.734m | 8.331ms | 6 | 10 | 60.00 | ||
| V2 | singlebit_err_counter | flash_ctrl_serr_counter | 1.299m | 2.776ms | 5 | 5 | 100.00 |
| V2 | singlebit_err_address | flash_ctrl_serr_address | 1.410m | 7.000ms | 5 | 5 | 100.00 |
| V2 | scramble | flash_ctrl_wo | 4.134m | 2.954ms | 19 | 20 | 95.00 |
| flash_ctrl_write_word_sweep | 15.350s | 149.679us | 1 | 1 | 100.00 | ||
| flash_ctrl_read_word_sweep | 14.120s | 81.541us | 1 | 1 | 100.00 | ||
| flash_ctrl_ro | 2.388m | 1.595ms | 19 | 20 | 95.00 | ||
| flash_ctrl_rw | 11.021m | 9.411ms | 18 | 20 | 90.00 | ||
| V2 | filesystem_support | flash_ctrl_fs_sup | 42.380s | 649.788us | 5 | 5 | 100.00 |
| V2 | rma_write_process_error | flash_ctrl_rma_err | 20.796m | 66.197ms | 3 | 3 | 100.00 |
| flash_ctrl_hw_prog_rma_wipe_err | 5.659m | 10.012ms | 20 | 20 | 100.00 | ||
| V2 | alert_test | flash_ctrl_alert_test | 14.810s | 135.799us | 50 | 50 | 100.00 |
| V2 | intr_test | flash_ctrl_intr_test | 14.050s | 17.164us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | flash_ctrl_tl_errors | 20.870s | 65.583us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | flash_ctrl_tl_errors | 20.870s | 65.583us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | flash_ctrl_csr_hw_reset | 46.350s | 104.003us | 5 | 5 | 100.00 |
| flash_ctrl_csr_rw | 17.670s | 55.333us | 20 | 20 | 100.00 | ||
| flash_ctrl_csr_aliasing | 1.118m | 9.324ms | 5 | 5 | 100.00 | ||
| flash_ctrl_same_csr_outstanding | 38.050s | 3.512ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | flash_ctrl_csr_hw_reset | 46.350s | 104.003us | 5 | 5 | 100.00 |
| flash_ctrl_csr_rw | 17.670s | 55.333us | 20 | 20 | 100.00 | ||
| flash_ctrl_csr_aliasing | 1.118m | 9.324ms | 5 | 5 | 100.00 | ||
| flash_ctrl_same_csr_outstanding | 38.050s | 3.512ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 983 | 1013 | 97.04 | |||
| V2S | shadow_reg_update_error | flash_ctrl_shadow_reg_errors | 16.270s | 36.701us | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | flash_ctrl_shadow_reg_errors | 16.270s | 36.701us | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | flash_ctrl_shadow_reg_errors | 16.270s | 36.701us | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | flash_ctrl_shadow_reg_errors | 16.270s | 36.701us | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | flash_ctrl_shadow_reg_errors_with_csr_rw | 15.930s | 61.270us | 20 | 20 | 100.00 |
| V2S | tl_intg_err | flash_ctrl_sec_cm | 1.719h | 8.323ms | 2 | 5 | 40.00 |
| flash_ctrl_tl_intg_err | 15.163m | 8.561ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_reg_bus_integrity | flash_ctrl_tl_intg_err | 15.163m | 8.561ms | 20 | 20 | 100.00 |
| V2S | sec_cm_host_bus_integrity | flash_ctrl_tl_intg_err | 15.163m | 8.561ms | 20 | 20 | 100.00 |
| V2S | sec_cm_mem_bus_integrity | flash_ctrl_rd_intg | 32.890s | 68.265us | 3 | 3 | 100.00 |
| flash_ctrl_wr_intg | 15.170s | 53.028us | 3 | 3 | 100.00 | ||
| V2S | sec_cm_scramble_key_sideload | flash_ctrl_smoke | 3.589m | 33.824us | 50 | 50 | 100.00 |
| V2S | sec_cm_lc_ctrl_intersig_mubi | flash_ctrl_otp_reset | 2.291m | 70.905us | 80 | 80 | 100.00 |
| flash_ctrl_disable | 22.550s | 119.234us | 50 | 50 | 100.00 | ||
| flash_ctrl_sec_info_access | 1.567m | 6.712ms | 50 | 50 | 100.00 | ||
| flash_ctrl_connect | 16.540s | 15.231us | 80 | 80 | 100.00 | ||
| V2S | sec_cm_ctrl_config_regwen | flash_ctrl_config_regwen | 14.010s | 226.289us | 5 | 5 | 100.00 |
| V2S | sec_cm_data_regions_config_regwen | flash_ctrl_csr_rw | 17.670s | 55.333us | 20 | 20 | 100.00 |
| V2S | sec_cm_data_regions_config_shadow | flash_ctrl_shadow_reg_errors | 16.270s | 36.701us | 20 | 20 | 100.00 |
| V2S | sec_cm_info_regions_config_regwen | flash_ctrl_csr_rw | 17.670s | 55.333us | 20 | 20 | 100.00 |
| V2S | sec_cm_info_regions_config_shadow | flash_ctrl_shadow_reg_errors | 16.270s | 36.701us | 20 | 20 | 100.00 |
| V2S | sec_cm_bank_config_regwen | flash_ctrl_csr_rw | 17.670s | 55.333us | 20 | 20 | 100.00 |
| V2S | sec_cm_bank_config_shadow | flash_ctrl_shadow_reg_errors | 16.270s | 36.701us | 20 | 20 | 100.00 |
| V2S | sec_cm_mem_ctrl_global_esc | flash_ctrl_disable | 22.550s | 119.234us | 50 | 50 | 100.00 |
| V2S | sec_cm_mem_ctrl_local_esc | flash_ctrl_rd_intg | 32.890s | 68.265us | 3 | 3 | 100.00 |
| flash_ctrl_access_after_disable | 13.870s | 45.198us | 3 | 3 | 100.00 | ||
| V2S | sec_cm_mem_disable_config_mubi | flash_ctrl_disable | 22.550s | 119.234us | 50 | 50 | 100.00 |
| V2S | sec_cm_exec_config_redun | flash_ctrl_fetch_code | 27.200s | 469.290us | 10 | 10 | 100.00 |
| V2S | sec_cm_mem_scramble | flash_ctrl_rw | 11.021m | 9.411ms | 18 | 20 | 90.00 |
| V2S | sec_cm_mem_integrity | flash_ctrl_rw_serr | 11.734m | 8.331ms | 6 | 10 | 60.00 |
| flash_ctrl_rw_derr | 12.732m | 4.596ms | 7 | 10 | 70.00 | ||
| flash_ctrl_integrity | 12.497m | 9.569ms | 3 | 5 | 60.00 | ||
| V2S | sec_cm_rma_entry_mem_sec_wipe | flash_ctrl_hw_rma | 34.183m | 169.004ms | 3 | 3 | 100.00 |
| V2S | sec_cm_ctrl_fsm_sparse | flash_ctrl_sec_cm | 1.719h | 8.323ms | 2 | 5 | 40.00 |
| V2S | sec_cm_phy_fsm_sparse | flash_ctrl_sec_cm | 1.719h | 8.323ms | 2 | 5 | 40.00 |
| V2S | sec_cm_phy_prog_fsm_sparse | flash_ctrl_sec_cm | 1.719h | 8.323ms | 2 | 5 | 40.00 |
| V2S | sec_cm_ctr_redun | flash_ctrl_sec_cm | 1.719h | 8.323ms | 2 | 5 | 40.00 |
| V2S | sec_cm_phy_arbiter_ctrl_redun | flash_ctrl_phy_arb_redun | 17.870s | 710.623us | 5 | 5 | 100.00 |
| V2S | sec_cm_phy_host_grant_ctrl_consistency | flash_ctrl_phy_host_grant_err | 14.190s | 24.253us | 5 | 5 | 100.00 |
| V2S | sec_cm_phy_ack_ctrl_consistency | flash_ctrl_phy_ack_consistency | 14.460s | 37.956us | 5 | 5 | 100.00 |
| V2S | sec_cm_fifo_ctr_redun | flash_ctrl_sec_cm | 1.719h | 8.323ms | 2 | 5 | 40.00 |
| V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | flash_ctrl_sec_cm | 1.719h | 8.323ms | 2 | 5 | 40.00 |
| V2S | sec_cm_prog_tl_lc_gate_fsm_sparse | flash_ctrl_sec_cm | 1.719h | 8.323ms | 2 | 5 | 40.00 |
| V2S | TOTAL | 141 | 144 | 97.92 | |||
| V3 | asymmetric_read_path | flash_ctrl_rd_ooo | 45.460s | 134.030us | 1 | 1 | 100.00 |
| V3 | stress_all_with_rand_reset | flash_ctrl_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 1 | 1 | 100.00 | |||
| TOTAL | 1245 | 1278 | 97.42 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 9 | 9 | 9 | 100.00 |
| V2 | 55 | 55 | 44 | 80.00 |
| V2S | 12 | 12 | 11 | 91.67 |
| V3 | 2 | 1 | 1 | 50.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 96.28 | 95.71 | 93.87 | 97.54 | 92.52 | 98.14 | 98.16 | 98.00 |
UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 10 failures:
8.flash_ctrl_rw_evict_all_en.114523505239247336565685347411071142195832254377350029994102370002320908967196
Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_rw_evict_all_en/latest/run.log
UVM_FATAL @ 9679.6 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x0007b470
UVM_INFO @ 9679.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.flash_ctrl_rw_evict_all_en.112785939821956291658137565279989180228803068747833757721438136537815873972541
Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/19.flash_ctrl_rw_evict_all_en/latest/run.log
UVM_FATAL @ 14786.8 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00002840
UVM_INFO @ 14786.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
15.flash_ctrl_rw_evict.33308361927737686564582116459477983793048423945714807883162304725520141427045
Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/15.flash_ctrl_rw_evict/latest/run.log
UVM_FATAL @ 98291.7 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00022660
UVM_INFO @ 98291.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.flash_ctrl_rw_evict.38625831286652794886297322094892406615591774536469946844744586902437114322618
Line 294, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/17.flash_ctrl_rw_evict/latest/run.log
UVM_FATAL @ 21896.6 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00016db8
UVM_INFO @ 21896.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:289) m_otf_scb [process_read] unexpected double bit error * has 5 failures:
Test flash_ctrl_read_word_sweep_derr has 3 failures.
0.flash_ctrl_read_word_sweep_derr.77919527594707839598661631901288705522026657151161550922485635530808978402450
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_read_word_sweep_derr/latest/run.log
UVM_ERROR @ 4898.4 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x000040e8
UVM_INFO @ 4898.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.flash_ctrl_read_word_sweep_derr.9211390754465193256149921307587148210028418189211293811670613374321440263583
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_read_word_sweep_derr/latest/run.log
UVM_ERROR @ 41141.4 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00000a08
UVM_INFO @ 41141.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test flash_ctrl_integrity has 1 failures.
3.flash_ctrl_integrity.5647513552789544360562746923756469484869844181010284243177763670683395226975
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_integrity/latest/run.log
UVM_ERROR @ 835777.0 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00004610
UVM_INFO @ 835777.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test flash_ctrl_rw_derr has 1 failures.
7.flash_ctrl_rw_derr.24484218529971415230107932582337092595878821389653669912853043582703682235702
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_rw_derr/latest/run.log
UVM_ERROR @ 1070295.4 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00003e00
UVM_INFO @ 1070295.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 4 failures:
Test flash_ctrl_read_word_sweep_serr has 1 failures.
3.flash_ctrl_read_word_sweep_serr.103528956997025674521453473264469041734910141720255762135098545492671572767629
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_read_word_sweep_serr/latest/run.log
UVM_ERROR @ 11491.1 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
UVM_INFO @ 11491.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test flash_ctrl_rw_serr has 1 failures.
7.flash_ctrl_rw_serr.78658445234461743091921957259109307111647541617023798409429341234677746703729
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_rw_serr/latest/run.log
UVM_ERROR @ 2657986.1 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
UVM_INFO @ 2657986.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test flash_ctrl_ro has 1 failures.
12.flash_ctrl_ro.72615828586270772637722574173598395396330880541013661573419486687980804750482
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_ro/latest/run.log
UVM_ERROR @ 237756.0 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
UVM_INFO @ 237756.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test flash_ctrl_rw has 1 failures.
13.flash_ctrl_rw.34785912207885253527321617967018370758723548088590762418014439641994352464017
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_rw/latest/run.log
UVM_ERROR @ 815274.3 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
UVM_INFO @ 815274.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 4 failures:
Test flash_ctrl_rw_derr has 2 failures.
4.flash_ctrl_rw_derr.53208473129536487496408411106323289066829793789534032176821512668458787721044
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw_derr/latest/run.log
Job ID: smart:18a2f87d-0f8f-4bae-8c2b-7770582aadfd
9.flash_ctrl_rw_derr.11508749730995927356863163820951474210527280618306052380271246892829665461654
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_rw_derr/latest/run.log
Job ID: smart:12b0fb3b-1503-4e73-a086-af060ae8baa6
Test flash_ctrl_wo has 1 failures.
7.flash_ctrl_wo.9107375304922693542812223381338168040123596387294268475475040296867457341988
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_wo/latest/run.log
Job ID: smart:ec1d2b86-4301-415c-a7f2-f958f683e187
Test flash_ctrl_rw has 1 failures.
16.flash_ctrl_rw.94116036573485426074244177179204929977393253175717957526755149457850913525250
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/16.flash_ctrl_rw/latest/run.log
Job ID: smart:ac13534a-3b71-4ded-929d-1ddfa8fe28be
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 3 failures:
Test flash_ctrl_rw_serr has 2 failures.
0.flash_ctrl_rw_serr.31495366328593868582729009035091692917292734010211385358040265902620574364798
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_serr/latest/run.log
UVM_ERROR @ 1287166.0 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (9684540966356280838176 [0x20d00012a01005e8820] vs 12045724207791103445024 [0x28d00012a01005e8820])
UVM_INFO @ 1287166.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.flash_ctrl_rw_serr.70822896799796606828523988790421450496815668868330968227851804254877061106166
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_rw_serr/latest/run.log
UVM_ERROR @ 1045614.5 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (451945379842047345680 [0x188000887504380410] vs 451945379842315781136 [0x188000887514380410])
UVM_INFO @ 1045614.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test flash_ctrl_integrity has 1 failures.
4.flash_ctrl_integrity.36432103057638886603379243686152371890056790898321514869917953991520443761065
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_integrity/latest/run.log
UVM_ERROR @ 3899658.4 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (963315457252249311248 [0x3438b00081c3501810] vs 5102591967782548605464 [0x1149cb04801e0410a18])
UVM_INFO @ 3899658.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$isunknown(rdata_o))' has 2 failures:
2.flash_ctrl_sec_cm.90106638213475182785596238131495524379477004848937659747427423370055733898966
Line 331, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_sec_cm/latest/run.log
Offending '(!$isunknown(rdata_o))'
UVM_ERROR @ 5957.6 ns: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 5957.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.flash_ctrl_sec_cm.71158119118589843185848574135373393387938021188368531866247455794791502741786
Line 647, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_sec_cm/latest/run.log
Offending '(!$isunknown(rdata_o))'
UVM_ERROR @ 513832.0 ns: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 513832.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$isunknown(mem_tl_o.d_valid))' has 1 failures:
1.flash_ctrl_sec_cm.73107535519069449617895635963362135653152711476223925661901546509874206639942
Line 297, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_sec_cm/latest/run.log
Offending '(!$isunknown(mem_tl_o.d_valid))'
UVM_ERROR @ 8588.8 ns: (flash_ctrl.sv:1378) [ASSERT FAILED] MemTlDValidKnownO_A
UVM_INFO @ 8588.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 1 failures:
3.flash_ctrl_rw_serr.66761179803361477243346315695413827269842710386740317714925533254111276379179
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_rw_serr/latest/run.log
UVM_ERROR @ 6880948.5 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (4134467933332668309664 [0xe02144c804211a60a0] vs 4134467933332668571808 [0xe02144c804211e60a0])
UVM_INFO @ 6880948.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp fc555def_3c871cd4:ffffffff_ffffffff mismatch!! has 1 failures:
25.flash_ctrl_intr_rd.99103293221627916290597554937618231184797764340713472536249913628413421548355
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/25.flash_ctrl_intr_rd/latest/run.log
UVM_ERROR @ 2660071.1 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] 1: obs:exp fc555def_3c871cd4:ffffffff_ffffffff mismatch!!
UVM_INFO @ 2660071.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp beff10e8_8f3f6127:ffffffff_8f3f* mismatch!! has 1 failures:
28.flash_ctrl_intr_rd.34071838994826611381004663740213053434196493856487174678315036363841685036640
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/28.flash_ctrl_intr_rd/latest/run.log
UVM_ERROR @ 170963.1 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] 5: obs:exp beff10e8_8f3f6127:ffffffff_8f3f6127 mismatch!!
UVM_INFO @ 170963.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *ceb47_00f3895b:ffffffff_00f3895b mismatch!! has 1 failures:
37.flash_ctrl_intr_rd.2879786268051482335882780433475882688250198308401578913815133796452489383237
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/37.flash_ctrl_intr_rd/latest/run.log
UVM_ERROR @ 11034620.6 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] 3: obs:exp 885ceb47_00f3895b:ffffffff_00f3895b mismatch!!
UVM_INFO @ 11034620.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---