f92a5ee77b
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | flash_ctrl_smoke | 4.061m | 1.402ms | 50 | 50 | 100.00 |
V1 | smoke_hw | flash_ctrl_smoke_hw | 26.540s | 27.873us | 5 | 5 | 100.00 |
V1 | csr_hw_reset | flash_ctrl_csr_hw_reset | 45.890s | 154.768us | 5 | 5 | 100.00 |
V1 | csr_rw | flash_ctrl_csr_rw | 17.770s | 99.882us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | flash_ctrl_csr_bit_bash | 1.141m | 661.812us | 5 | 5 | 100.00 |
V1 | csr_aliasing | flash_ctrl_csr_aliasing | 1.073m | 2.754ms | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | flash_ctrl_csr_mem_rw_with_rand_reset | 19.530s | 158.594us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | flash_ctrl_csr_rw | 17.770s | 99.882us | 20 | 20 | 100.00 |
flash_ctrl_csr_aliasing | 1.073m | 2.754ms | 5 | 5 | 100.00 | ||
V1 | mem_walk | flash_ctrl_mem_walk | 13.840s | 15.027us | 5 | 5 | 100.00 |
V1 | mem_partial_access | flash_ctrl_mem_partial_access | 13.600s | 51.780us | 5 | 5 | 100.00 |
V1 | TOTAL | 120 | 120 | 100.00 | |||
V2 | sw_op | flash_ctrl_sw_op | 26.630s | 30.444us | 5 | 5 | 100.00 |
V2 | host_read_direct | flash_ctrl_host_dir_rd | 2.083m | 353.034us | 5 | 5 | 100.00 |
V2 | rma_hw_if | flash_ctrl_hw_rma | 41.349m | 1.590s | 3 | 3 | 100.00 |
flash_ctrl_hw_rma_reset | 19.055m | 380.257ms | 20 | 20 | 100.00 | ||
flash_ctrl_lcmgr_intg | 14.070s | 65.601us | 20 | 20 | 100.00 | ||
V2 | host_controller_arb | flash_ctrl_host_ctrl_arb | 45.631m | 267.487ms | 5 | 5 | 100.00 |
V2 | erase_suspend | flash_ctrl_erase_suspend | 10.402m | 21.056ms | 5 | 5 | 100.00 |
V2 | program_reset | flash_ctrl_prog_reset | 3.694m | 5.166ms | 30 | 30 | 100.00 |
V2 | full_memory_access | flash_ctrl_full_mem_access | 1.287h | 101.740ms | 5 | 5 | 100.00 |
V2 | rd_buff_eviction | flash_ctrl_rd_buff_evict | 4.280m | 2.050ms | 5 | 5 | 100.00 |
V2 | rd_buff_eviction_w_ecc | flash_ctrl_rw_evict | 32.360s | 52.934us | 27 | 40 | 67.50 |
flash_ctrl_rw_evict_all_en | 32.290s | 83.274us | 35 | 40 | 87.50 | ||
flash_ctrl_re_evict | 37.200s | 162.817us | 20 | 20 | 100.00 | ||
V2 | host_arb | flash_ctrl_phy_arb | 9.443m | 1.393ms | 20 | 20 | 100.00 |
V2 | host_interleave | flash_ctrl_phy_arb | 9.443m | 1.393ms | 20 | 20 | 100.00 |
V2 | memory_protection | flash_ctrl_mp_regions | 18.756m | 24.426ms | 19 | 20 | 95.00 |
V2 | fetch_code | flash_ctrl_fetch_code | 33.060s | 612.519us | 10 | 10 | 100.00 |
V2 | all_partitions | flash_ctrl_rand_ops | 19.693m | 18.579ms | 20 | 20 | 100.00 |
V2 | error_mp | flash_ctrl_error_mp | 43.018m | 20.700ms | 10 | 10 | 100.00 |
V2 | error_prog_win | flash_ctrl_error_prog_win | 15.546m | 911.990us | 10 | 10 | 100.00 |
V2 | error_prog_type | flash_ctrl_error_prog_type | 47.691m | 959.837us | 5 | 5 | 100.00 |
V2 | error_read_seed | flash_ctrl_hw_read_seed_err | 13.770s | 33.174us | 20 | 20 | 100.00 |
V2 | read_write_overflow | flash_ctrl_oversize_error | 3.855m | 3.675ms | 5 | 5 | 100.00 |
V2 | flash_ctrl_disable | flash_ctrl_disable | 22.710s | 23.542us | 50 | 50 | 100.00 |
V2 | flash_ctrl_connect | flash_ctrl_connect | 16.630s | 16.062us | 80 | 80 | 100.00 |
V2 | stress_all | flash_ctrl_stress_all | 26.137m | 1.547ms | 5 | 5 | 100.00 |
V2 | secret_partition | flash_ctrl_hw_sec_otp | 4.099m | 4.515ms | 50 | 50 | 100.00 |
flash_ctrl_otp_reset | 2.290m | 124.347us | 80 | 80 | 100.00 | ||
V2 | isolation_partition | flash_ctrl_hw_rma | 41.349m | 1.590s | 3 | 3 | 100.00 |
V2 | interrupts | flash_ctrl_intr_rd | 5.648m | 3.640ms | 38 | 40 | 95.00 |
flash_ctrl_intr_wr | 1.735m | 35.369ms | 10 | 10 | 100.00 | ||
flash_ctrl_intr_rd_slow_flash | 8.221m | 34.061ms | 40 | 40 | 100.00 | ||
flash_ctrl_intr_wr_slow_flash | 4.466m | 102.931ms | 10 | 10 | 100.00 | ||
V2 | invalid_op | flash_ctrl_invalid_op | 1.624m | 3.892ms | 20 | 20 | 100.00 |
V2 | mid_op_rst | flash_ctrl_mid_op_rst | 1.305m | 2.477ms | 5 | 5 | 100.00 |
V2 | double_bit_err | flash_ctrl_read_word_sweep_derr | 22.730s | 59.022us | 5 | 5 | 100.00 |
flash_ctrl_ro_derr | 2.993m | 934.073us | 10 | 10 | 100.00 | ||
flash_ctrl_rw_derr | 14.623m | 9.660ms | 8 | 10 | 80.00 | ||
flash_ctrl_derr_detect | 1.805m | 367.882us | 5 | 5 | 100.00 | ||
flash_ctrl_integrity | 13.257m | 4.755ms | 4 | 5 | 80.00 | ||
V2 | single_bit_err | flash_ctrl_read_word_sweep_serr | 22.870s | 91.688us | 3 | 5 | 60.00 |
flash_ctrl_ro_serr | 2.844m | 3.191ms | 10 | 10 | 100.00 | ||
flash_ctrl_rw_serr | 13.087m | 4.922ms | 5 | 10 | 50.00 | ||
V2 | singlebit_err_counter | flash_ctrl_serr_counter | 1.597m | 3.264ms | 5 | 5 | 100.00 |
V2 | singlebit_err_address | flash_ctrl_serr_address | 1.883m | 5.307ms | 5 | 5 | 100.00 |
V2 | scramble | flash_ctrl_wo | 4.441m | 3.405ms | 19 | 20 | 95.00 |
flash_ctrl_write_word_sweep | 16.630s | 240.292us | 1 | 1 | 100.00 | ||
flash_ctrl_read_word_sweep | 14.300s | 53.955us | 1 | 1 | 100.00 | ||
flash_ctrl_ro | 2.762m | 2.351ms | 20 | 20 | 100.00 | ||
flash_ctrl_rw | 12.483m | 41.187ms | 20 | 20 | 100.00 | ||
V2 | filesystem_support | flash_ctrl_fs_sup | 44.070s | 345.241us | 5 | 5 | 100.00 |
V2 | rma_write_process_error | flash_ctrl_rma_err | 16.389m | 40.556ms | 3 | 3 | 100.00 |
flash_ctrl_hw_prog_rma_wipe_err | 5.695m | 10.012ms | 20 | 20 | 100.00 | ||
V2 | alert_test | flash_ctrl_alert_test | 14.540s | 393.002us | 50 | 50 | 100.00 |
V2 | intr_test | flash_ctrl_intr_test | 14.010s | 18.898us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | flash_ctrl_tl_errors | 21.260s | 434.855us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | flash_ctrl_tl_errors | 21.260s | 434.855us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | flash_ctrl_csr_hw_reset | 45.890s | 154.768us | 5 | 5 | 100.00 |
flash_ctrl_csr_rw | 17.770s | 99.882us | 20 | 20 | 100.00 | ||
flash_ctrl_csr_aliasing | 1.073m | 2.754ms | 5 | 5 | 100.00 | ||
flash_ctrl_same_csr_outstanding | 35.740s | 1.275ms | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | flash_ctrl_csr_hw_reset | 45.890s | 154.768us | 5 | 5 | 100.00 |
flash_ctrl_csr_rw | 17.770s | 99.882us | 20 | 20 | 100.00 | ||
flash_ctrl_csr_aliasing | 1.073m | 2.754ms | 5 | 5 | 100.00 | ||
flash_ctrl_same_csr_outstanding | 35.740s | 1.275ms | 20 | 20 | 100.00 | ||
V2 | TOTAL | 981 | 1013 | 96.84 | |||
V2S | shadow_reg_update_error | flash_ctrl_shadow_reg_errors | 15.960s | 14.841us | 20 | 20 | 100.00 |
V2S | shadow_reg_read_clear_staged_value | flash_ctrl_shadow_reg_errors | 15.960s | 14.841us | 20 | 20 | 100.00 |
V2S | shadow_reg_storage_error | flash_ctrl_shadow_reg_errors | 15.960s | 14.841us | 20 | 20 | 100.00 |
V2S | shadowed_reset_glitch | flash_ctrl_shadow_reg_errors | 15.960s | 14.841us | 20 | 20 | 100.00 |
V2S | shadow_reg_update_error_with_csr_rw | flash_ctrl_shadow_reg_errors_with_csr_rw | 15.820s | 24.898us | 20 | 20 | 100.00 |
V2S | tl_intg_err | flash_ctrl_sec_cm | 1.766h | 3.018ms | 2 | 5 | 40.00 |
flash_ctrl_tl_intg_err | 15.277m | 650.534us | 20 | 20 | 100.00 | ||
V2S | sec_cm_reg_bus_integrity | flash_ctrl_tl_intg_err | 15.277m | 650.534us | 20 | 20 | 100.00 |
V2S | sec_cm_host_bus_integrity | flash_ctrl_tl_intg_err | 15.277m | 650.534us | 20 | 20 | 100.00 |
V2S | sec_cm_mem_bus_integrity | flash_ctrl_rd_intg | 32.970s | 218.327us | 3 | 3 | 100.00 |
flash_ctrl_wr_intg | 16.050s | 289.090us | 3 | 3 | 100.00 | ||
V2S | sec_cm_scramble_key_sideload | flash_ctrl_smoke | 4.061m | 1.402ms | 50 | 50 | 100.00 |
V2S | sec_cm_lc_ctrl_intersig_mubi | flash_ctrl_otp_reset | 2.290m | 124.347us | 80 | 80 | 100.00 |
flash_ctrl_disable | 22.710s | 23.542us | 50 | 50 | 100.00 | ||
flash_ctrl_sec_info_access | 1.462m | 9.839ms | 50 | 50 | 100.00 | ||
flash_ctrl_connect | 16.630s | 16.062us | 80 | 80 | 100.00 | ||
V2S | sec_cm_ctrl_config_regwen | flash_ctrl_config_regwen | 13.970s | 69.396us | 5 | 5 | 100.00 |
V2S | sec_cm_data_regions_config_regwen | flash_ctrl_csr_rw | 17.770s | 99.882us | 20 | 20 | 100.00 |
V2S | sec_cm_data_regions_config_shadow | flash_ctrl_shadow_reg_errors | 15.960s | 14.841us | 20 | 20 | 100.00 |
V2S | sec_cm_info_regions_config_regwen | flash_ctrl_csr_rw | 17.770s | 99.882us | 20 | 20 | 100.00 |
V2S | sec_cm_info_regions_config_shadow | flash_ctrl_shadow_reg_errors | 15.960s | 14.841us | 20 | 20 | 100.00 |
V2S | sec_cm_bank_config_regwen | flash_ctrl_csr_rw | 17.770s | 99.882us | 20 | 20 | 100.00 |
V2S | sec_cm_bank_config_shadow | flash_ctrl_shadow_reg_errors | 15.960s | 14.841us | 20 | 20 | 100.00 |
V2S | sec_cm_mem_ctrl_global_esc | flash_ctrl_disable | 22.710s | 23.542us | 50 | 50 | 100.00 |
V2S | sec_cm_mem_ctrl_local_esc | flash_ctrl_rd_intg | 32.970s | 218.327us | 3 | 3 | 100.00 |
flash_ctrl_access_after_disable | 14.080s | 14.150us | 3 | 3 | 100.00 | ||
V2S | sec_cm_mem_disable_config_mubi | flash_ctrl_disable | 22.710s | 23.542us | 50 | 50 | 100.00 |
V2S | sec_cm_exec_config_redun | flash_ctrl_fetch_code | 33.060s | 612.519us | 10 | 10 | 100.00 |
V2S | sec_cm_mem_scramble | flash_ctrl_rw | 12.483m | 41.187ms | 20 | 20 | 100.00 |
V2S | sec_cm_mem_integrity | flash_ctrl_rw_serr | 13.087m | 4.922ms | 5 | 10 | 50.00 |
flash_ctrl_rw_derr | 14.623m | 9.660ms | 8 | 10 | 80.00 | ||
flash_ctrl_integrity | 13.257m | 4.755ms | 4 | 5 | 80.00 | ||
V2S | sec_cm_rma_entry_mem_sec_wipe | flash_ctrl_hw_rma | 41.349m | 1.590s | 3 | 3 | 100.00 |
V2S | sec_cm_ctrl_fsm_sparse | flash_ctrl_sec_cm | 1.766h | 3.018ms | 2 | 5 | 40.00 |
V2S | sec_cm_phy_fsm_sparse | flash_ctrl_sec_cm | 1.766h | 3.018ms | 2 | 5 | 40.00 |
V2S | sec_cm_phy_prog_fsm_sparse | flash_ctrl_sec_cm | 1.766h | 3.018ms | 2 | 5 | 40.00 |
V2S | sec_cm_ctr_redun | flash_ctrl_sec_cm | 1.766h | 3.018ms | 2 | 5 | 40.00 |
V2S | sec_cm_phy_arbiter_ctrl_redun | flash_ctrl_phy_arb_redun | 21.560s | 728.029us | 5 | 5 | 100.00 |
V2S | sec_cm_phy_host_grant_ctrl_consistency | flash_ctrl_phy_host_grant_err | 14.390s | 15.445us | 5 | 5 | 100.00 |
V2S | sec_cm_phy_ack_ctrl_consistency | flash_ctrl_phy_ack_consistency | 15.020s | 87.537us | 5 | 5 | 100.00 |
V2S | sec_cm_fifo_ctr_redun | flash_ctrl_sec_cm | 1.766h | 3.018ms | 2 | 5 | 40.00 |
V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | flash_ctrl_sec_cm | 1.766h | 3.018ms | 2 | 5 | 40.00 |
V2S | sec_cm_prog_tl_lc_gate_fsm_sparse | flash_ctrl_sec_cm | 1.766h | 3.018ms | 2 | 5 | 40.00 |
V2S | TOTAL | 141 | 144 | 97.92 | |||
V3 | asymmetric_read_path | flash_ctrl_rd_ooo | 46.580s | 217.672us | 1 | 1 | 100.00 |
V3 | stress_all_with_rand_reset | flash_ctrl_stress_all_with_rand_reset | 0 | 0 | -- | ||
V3 | TOTAL | 1 | 1 | 100.00 | |||
TOTAL | 1243 | 1278 | 97.26 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 9 | 9 | 9 | 100.00 |
V2 | 55 | 55 | 46 | 83.64 |
V2S | 12 | 12 | 11 | 91.67 |
V3 | 2 | 1 | 1 | 50.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
96.33 | 95.73 | 94.09 | 97.54 | 92.52 | 98.17 | 98.16 | 98.09 |
UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address *
has 17 failures:
2.flash_ctrl_rw_evict.27232991872020769178935305919447387755696602078794233633366615227694427597839
Line 292, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rw_evict/latest/run.log
UVM_FATAL @ 23419.5 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00084340
UVM_INFO @ 23419.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.flash_ctrl_rw_evict.313266337379478230069377725629506865560206590571838132335057799345643177065
Line 290, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_rw_evict/latest/run.log
UVM_FATAL @ 82113.3 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00003558
UVM_INFO @ 82113.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
2.flash_ctrl_rw_evict_all_en.96353833127152621970796705626116548224238831128478598255700696734039867687828
Line 292, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rw_evict_all_en/latest/run.log
UVM_FATAL @ 20486.2 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00004bc0
UVM_INFO @ 20486.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.flash_ctrl_rw_evict_all_en.53489200558007210324083262098995764288322689785634798778088360886764796746683
Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_rw_evict_all_en/latest/run.log
UVM_FATAL @ 24962.7 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x000041e0
UVM_INFO @ 24962.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*])
has 4 failures:
Test flash_ctrl_rw_serr has 2 failures.
0.flash_ctrl_rw_serr.36310893674078585865913328272973566861162221337921523044984851861944623612498
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_serr/latest/run.log
UVM_ERROR @ 9971864.8 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (7084774862059473240344 [0x1801100904c10048118] vs 7084774862059474288920 [0x1801100904c10148118])
UVM_INFO @ 9971864.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.flash_ctrl_rw_serr.51734137684981030230747560610966389170229668058223378828122125708170741240029
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_serr/latest/run.log
UVM_ERROR @ 3362622.3 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (56742617718849796052628 [0xc040602240544001694] vs 56742617736441982097044 [0xc040602340544001694])
UVM_INFO @ 3362622.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test flash_ctrl_rw_derr has 2 failures.
1.flash_ctrl_rw_derr.34258911286601568605898528338710488819879815601509805350688135804786918697885
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_derr/latest/run.log
UVM_ERROR @ 10819215.5 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (9481645924485315977216 [0x20200452c6801806000] vs 9481645924485299200000 [0x20200452c6800806000])
UVM_INFO @ 10819215.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.flash_ctrl_rw_derr.93285841753644182513430814112611985456908649698062517565230305132753592751399
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_rw_derr/latest/run.log
UVM_ERROR @ 9963865.0 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (2739381535457664860789 [0x94808e40a222408275] vs 2739381535457665909365 [0x94808e40a222508275])
UVM_INFO @ 9963865.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$isunknown(rdata_o))'
has 2 failures:
0.flash_ctrl_sec_cm.109490635523594656363912217791247817717596449770384688363235338411856207761171
Line 413, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_sec_cm/latest/run.log
Offending '(!$isunknown(rdata_o))'
UVM_ERROR @ 110163.8 ns: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 110163.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.flash_ctrl_sec_cm.110757287047774377599379651599186076844218190494273120291519765426619888279068
Line 325, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_sec_cm/latest/run.log
Offending '(!$isunknown(rdata_o))'
UVM_ERROR @ 24425.5 ns: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 24425.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job.
has 2 failures:
Test flash_ctrl_wo has 1 failures.
1.flash_ctrl_wo.8405317686480751376252134584823162003868412460282512002775641321151089175352
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_wo/latest/run.log
Job ID: smart:b676df6f-87d0-4d21-9e84-f67da5056d01
Test flash_ctrl_rw_serr has 1 failures.
3.flash_ctrl_rw_serr.19818281511710215727435162960366574258379805228727781325872359359737067648854
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_rw_serr/latest/run.log
Job ID: smart:8ed1f6b2-41eb-4fc0-8f53-041fcb4fcbbd
UVM_FATAL (flash_ctrl_mp_regions_vseq.sv:196) [flash_ctrl_mp_regions_vseq] wait timeout for alert_count == exp_alertcnt after do_mp_reg() alert_cnt:* exp_alert_cnt:*
has 1 failures:
1.flash_ctrl_mp_regions.13795372480385982911705014822507593729763160369286094071551173433877900919142
Line 892, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_mp_regions/latest/run.log
UVM_FATAL @ 2355750.3 ns: (flash_ctrl_mp_regions_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.flash_ctrl_mp_regions_vseq] wait timeout for alert_count == exp_alertcnt after do_mp_reg() alert_cnt:36 exp_alert_cnt:37
UVM_INFO @ 2355750.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly
has 1 failures:
2.flash_ctrl_read_word_sweep_serr.49890039400005528749580815150778697032127006853563618729311671350899060876306
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_read_word_sweep_serr/latest/run.log
UVM_ERROR @ 5393.6 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
UVM_INFO @ 5393.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_base_vseq.sv:362) [flash_ctrl_rw_vseq] Check failed (*) Too many unsuccessful attempts to create a prog_op
has 1 failures:
2.flash_ctrl_rw_serr.80720245034393351787037559399902824955898483750442078493116108098406592306742
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rw_serr/latest/run.log
UVM_ERROR @ 9293629.8 ns: (flash_ctrl_otf_base_vseq.sv:362) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_vseq] Check failed (0) Too many unsuccessful attempts to create a prog_op
UVM_INFO @ 9293629.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$isunknown(mem_tl_o.d_valid))'
has 1 failures:
2.flash_ctrl_sec_cm.113566182654181432647963091877109233038478357583508131431223355291201628911166
Line 331, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_sec_cm/latest/run.log
Offending '(!$isunknown(mem_tl_o.d_valid))'
UVM_ERROR @ 20395.6 ns: (flash_ctrl.sv:1378) [ASSERT FAILED] MemTlDValidKnownO_A
UVM_INFO @ 20395.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:289) m_otf_scb [process_read] unexpected double bit error *
has 1 failures:
3.flash_ctrl_integrity.99792425805675902875461916342362022901674981864839343071583354778869844474223
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_integrity/latest/run.log
UVM_ERROR @ 12666763.1 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00004408
UVM_INFO @ 12666763.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_err triggered unexpectedly
has 1 failures:
4.flash_ctrl_read_word_sweep_serr.22249727619120375561726826032553701630212104208551041224615192961558222783235
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_read_word_sweep_serr/latest/run.log
UVM_ERROR @ 5167.3 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_err triggered unexpectedly
UVM_INFO @ 5167.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*])
has 1 failures:
7.flash_ctrl_rw_serr.98405959706662377486708585524055052858219328440325936997093723983374410031792
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_rw_serr/latest/run.log
UVM_ERROR @ 2253603.8 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (11817664163736428233378 [0x280a3092040058442a2] vs 11817664163736428232866 [0x280a3092040058440a2])
UVM_INFO @ 2253603.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: *
has 1 failures:
18.flash_ctrl_rw_evict.99654622411072685384665657604107245509747176092638294838931833811584052502753
Line 295, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/18.flash_ctrl_rw_evict/latest/run.log
UVM_ERROR @ 9958.0 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
UVM_INFO @ 9958.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *eeb689f_ba44aaf1:ffffffff_ba44aaf* mismatch!!
has 1 failures:
31.flash_ctrl_intr_rd.33633505115117057895313440673775402372921063413497309521229563534910099962302
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/31.flash_ctrl_intr_rd/latest/run.log
UVM_ERROR @ 3492006.7 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] 0: obs:exp 8eeb689f_ba44aaf1:ffffffff_ba44aaf1 mismatch!!
UVM_INFO @ 3492006.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *a4fc290_8c6df625:ffffffff_8c6df* mismatch!!
has 1 failures:
36.flash_ctrl_intr_rd.100441851353531967020134456743313427172667888508863505934400864437132867585480
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/36.flash_ctrl_intr_rd/latest/run.log
UVM_ERROR @ 1294379.8 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] 5: obs:exp 9a4fc290_8c6df625:ffffffff_8c6df625 mismatch!!
UVM_INFO @ 1294379.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---