FLASH_CTRL Simulation Results

Monday June 10 2024 23:28:43 UTC

GitHub Revision: `a8c9c17a8c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 72227341233107832543509484606850665418885932500709631655793413524197290927900

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	4.118m	3.259ms	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.030s	29.889us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	46.160s	519.037us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.460s	26.944us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.520m	12.869ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.166m	3.260ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	20.850s	45.536us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.460s	26.944us	20	20	100.00
		flash_ctrl_csr_aliasing	1.166m	3.260ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.390s	160.725us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.490s	16.845us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.680s	71.953us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	1.316m	47.977us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	33.183m	125.473ms	3	3	100.00
		flash_ctrl_hw_rma_reset	18.610m	320.245ms	20	20	100.00
		flash_ctrl_lcmgr_intg	14.060s	15.458us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	47.131m	241.617ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	10.199m	8.331ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	3.991m	11.892ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.373h	698.457ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.588m	1.461ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	32.180s	82.745us	26	40	65.00
		flash_ctrl_rw_evict_all_en	32.070s	32.126us	38	40	95.00
		flash_ctrl_re_evict	39.590s	515.751us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	10.598m	2.130ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	10.598m	2.130ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	24.782m	18.958ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	29.520s	884.761us	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	22.655m	835.928us	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	41.333m	17.901ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	17.954m	850.175us	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	42.548m	558.189us	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	13.820s	131.281us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.730m	10.820ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	23.030s	24.465us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.530s	53.750us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	19.708m	3.658ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.271m	11.896ms	50	50	100.00
		flash_ctrl_otp_reset	2.257m	123.368us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	33.183m	125.473ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	4.047m	1.504ms	40	40	100.00
		flash_ctrl_intr_wr	1.535m	11.791ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	7.509m	29.022ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	5.267m	145.535ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.495m	4.191ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.238m	13.667ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	22.470s	32.305us	4	5	80.00
		flash_ctrl_ro_derr	2.950m	4.724ms	10	10	100.00
		flash_ctrl_rw_derr	12.414m	44.734ms	8	10	80.00
		flash_ctrl_derr_detect	1.757m	498.394us	5	5	100.00
		flash_ctrl_integrity	13.372m	4.772ms	4	5	80.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	22.840s	26.464us	5	5	100.00
		flash_ctrl_ro_serr	2.480m	1.351ms	10	10	100.00
		flash_ctrl_rw_serr	12.103m	5.664ms	8	10	80.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.196m	745.770us	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.842m	1.082ms	5	5	100.00
V2	scramble	flash_ctrl_wo	3.519m	2.493ms	20	20	100.00
		flash_ctrl_write_word_sweep	15.190s	152.949us	1	1	100.00
		flash_ctrl_read_word_sweep	14.380s	64.894us	1	1	100.00
		flash_ctrl_ro	2.641m	680.775us	20	20	100.00
		flash_ctrl_rw	11.019m	67.475ms	18	20	90.00
V2	filesystem_support	flash_ctrl_fs_sup	41.350s	410.972us	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	18.639m	365.666ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.724m	10.011ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.420s	52.977us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	13.940s	50.096us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	20.760s	254.185us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	20.760s	254.185us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	46.160s	519.037us	5	5	100.00
		flash_ctrl_csr_rw	17.460s	26.944us	20	20	100.00
		flash_ctrl_csr_aliasing	1.166m	3.260ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.370s	756.182us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	46.160s	519.037us	5	5	100.00
		flash_ctrl_csr_rw	17.460s	26.944us	20	20	100.00
		flash_ctrl_csr_aliasing	1.166m	3.260ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.370s	756.182us	20	20	100.00
V2		TOTAL			989	1013	97.63
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.160s	14.398us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.160s	14.398us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.160s	14.398us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.160s	14.398us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.300s	18.579us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.776h	20.734ms	2	5	40.00
		flash_ctrl_tl_intg_err	15.331m	2.708ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.331m	2.708ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.331m	2.708ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	31.730s	233.352us	3	3	100.00
		flash_ctrl_wr_intg	15.340s	48.842us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	4.118m	3.259ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.257m	123.368us	80	80	100.00
		flash_ctrl_disable	23.030s	24.465us	50	50	100.00
		flash_ctrl_sec_info_access	1.539m	1.551ms	50	50	100.00
		flash_ctrl_connect	16.530s	53.750us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	13.900s	22.584us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.460s	26.944us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.160s	14.398us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.460s	26.944us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.160s	14.398us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.460s	26.944us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.160s	14.398us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	23.030s	24.465us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	31.730s	233.352us	3	3	100.00
		flash_ctrl_access_after_disable	13.630s	147.192us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	23.030s	24.465us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	29.520s	884.761us	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	11.019m	67.475ms	18	20	90.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	12.103m	5.664ms	8	10	80.00
		flash_ctrl_rw_derr	12.414m	44.734ms	8	10	80.00
		flash_ctrl_integrity	13.372m	4.772ms	4	5	80.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	33.183m	125.473ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.776h	20.734ms	2	5	40.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.776h	20.734ms	2	5	40.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.776h	20.734ms	2	5	40.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.776h	20.734ms	2	5	40.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	22.510s	745.781us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.000s	15.419us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.360s	25.315us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.776h	20.734ms	2	5	40.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.776h	20.734ms	2	5	40.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.776h	20.734ms	2	5	40.00
V2S		TOTAL			141	144	97.92
V3	asymmetric_read_path	flash_ctrl_rd_ooo	43.270s	153.875us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1251	1278	97.89

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	48	87.27
V2S	12	12	11	91.67
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.05	95.24	93.87	97.54	92.52	97.06	98.06	98.09

Failure Buckets

UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 15 failures:

Test flash_ctrl_rw_evict has 14 failures.

3.flash_ctrl_rw_evict.53463821308758679421466994744929084786703016090129255758584664265592190335948
Line 294, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_rw_evict/latest/run.log

  UVM_FATAL @ 19753.2 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00000570
  UVM_INFO @ 19753.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.flash_ctrl_rw_evict.74350520081203249688392447218089063022004695715220243169326389051164694414358
Line 291, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw_evict/latest/run.log

  UVM_FATAL @ 89420.2 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00035060
  UVM_INFO @ 89420.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 12 more failures.

Test flash_ctrl_rw_evict_all_en has 1 failures.

30.flash_ctrl_rw_evict_all_en.75766144247517712492326307076606087666157610422144418862145740033860155846379
Line 287, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/30.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_FATAL @ 94626.3 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00003b10
  UVM_INFO @ 94626.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 3 failures:
- Test flash_ctrl_rw_serr has 1 failures.
  - 2.flash_ctrl_rw_serr.67590470066456984803371584051020703415846474469170123158556330390190690246328
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rw_serr/latest/run.log
```
  Job ID: smart:40605afc-dfb7-4e80-ae5e-045ee5263f6b
```
- Test flash_ctrl_rw has 2 failures.
  - 17.flash_ctrl_rw.62738030371001242254924343678574302649344448825197779140393123191770557548597
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/17.flash_ctrl_rw/latest/run.log
```
  Job ID: smart:53690709-351d-4082-950d-574bcce4a657
```
  - 19.flash_ctrl_rw.31259930812036523971231408019960767643098133906066653871767112433367603589973
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/19.flash_ctrl_rw/latest/run.log
```
  Job ID: smart:b2c33b47-add9-4350-a320-816b51b2be86
```

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 2 failures:

Test flash_ctrl_integrity has 1 failures.

1.flash_ctrl_integrity.44389855245269108995112689838138882314722843221088639693470370185999087310349
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_integrity/latest/run.log

  UVM_ERROR @ 2468106.2 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (23982046530912892557314 [0x51411c0c18980011802] vs 43903431182144667388200 [0x94c028081d01d000928])
  UVM_INFO @ 2468106.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_rw_derr has 1 failures.

2.flash_ctrl_rw_derr.40883246013126752637325732888437432622437934104770617248813702407038034661191
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rw_derr/latest/run.log

  UVM_ERROR @ 5503357.8 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (591647192618251585076 [0x2012c1130150000634] vs 591647190419228329524 [0x2012c1110150000634])
  UVM_INFO @ 5503357.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Offending '(!$isunknown(rdata_o))' has 2 failures:
- Test flash_ctrl_sec_cm has 2 failures.
  - 2.flash_ctrl_sec_cm.82638604285373686515852637107679523640795594832027067073217680575478045773398
    Line 449, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_sec_cm/latest/run.log
```
      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @ 118686.7 ns: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @ 118686.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 4.flash_ctrl_sec_cm.104277836718206421368278047756659376467788884805408162238658735541907511601313
    Line 297, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_sec_cm/latest/run.log
```
      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @ 9349.1 ns: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @ 9349.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$isunknown(mem_tl_o.d_valid))' has 1 failures:
- Test flash_ctrl_sec_cm has 1 failures.
  - 0.flash_ctrl_sec_cm.92283190086870245823740967609237499981475133391469534237906380596090252750543
    Line 345, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_sec_cm/latest/run.log
```
      Offending '(!$isunknown(mem_tl_o.d_valid))'
  UVM_ERROR @ 37520.8 ns: (flash_ctrl.sv:1378) [ASSERT FAILED] MemTlDValidKnownO_A
  UVM_INFO @ 37520.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 1 failures:
- Test flash_ctrl_rw_serr has 1 failures.
  - 1.flash_ctrl_rw_serr.100200228096496785758604036161917474876918795566373630385817477466774517524385
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_serr/latest/run.log
```
  UVM_ERROR @ 4632757.7 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (865296412022149380 [0xc02268090001104] vs 865296412022149412 [0xc02268090001124])
  UVM_INFO @ 4632757.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:289) m_otf_scb [process_read] unexpected double bit error * has 1 failures:
- Test flash_ctrl_read_word_sweep_derr has 1 failures.
  - 3.flash_ctrl_read_word_sweep_derr.41361119729883040364886838786002691645504958790286596948025024753707721388604
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_read_word_sweep_derr/latest/run.log
```
  UVM_ERROR @ 7122.8 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x0008acd0
  UVM_INFO @ 7122.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_base_vseq.sv:362) [flash_ctrl_rw_vseq] Check failed (*) Too many unsuccessful attempts to create a prog_op has 1 failures:
- Test flash_ctrl_rw_derr has 1 failures.
  - 4.flash_ctrl_rw_derr.18823030725699119061379236169376956742993522619687755602478075110007911515779
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 7479976.3 ns: (flash_ctrl_otf_base_vseq.sv:362) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_vseq] Check failed (0) Too many unsuccessful attempts to create a prog_op
  UVM_INFO @ 7479976.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 1 failures:
- Test flash_ctrl_rw_evict_all_en has 1 failures.
  - 34.flash_ctrl_rw_evict_all_en.112233317685701264869293724871183502490279664276682528577577364367424800404548
    Line 295, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/34.flash_ctrl_rw_evict_all_en/latest/run.log
```
  UVM_ERROR @ 24197.0 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 24197.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```