dd5ad5fb77| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | flash_ctrl_smoke | 4.865m | 5.246ms | 50 | 50 | 100.00 |
| V1 | smoke_hw | flash_ctrl_smoke_hw | 25.760s | 31.923us | 5 | 5 | 100.00 |
| V1 | csr_hw_reset | flash_ctrl_csr_hw_reset | 45.310s | 45.451us | 5 | 5 | 100.00 |
| V1 | csr_rw | flash_ctrl_csr_rw | 17.870s | 247.130us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | flash_ctrl_csr_bit_bash | 1.569m | 12.415ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | flash_ctrl_csr_aliasing | 1.116m | 5.076ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | flash_ctrl_csr_mem_rw_with_rand_reset | 19.730s | 114.180us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | flash_ctrl_csr_rw | 17.870s | 247.130us | 20 | 20 | 100.00 |
| flash_ctrl_csr_aliasing | 1.116m | 5.076ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | flash_ctrl_mem_walk | 13.480s | 64.025us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | flash_ctrl_mem_partial_access | 13.550s | 34.056us | 5 | 5 | 100.00 |
| V1 | TOTAL | 120 | 120 | 100.00 | |||
| V2 | sw_op | flash_ctrl_sw_op | 26.470s | 47.054us | 5 | 5 | 100.00 |
| V2 | host_read_direct | flash_ctrl_host_dir_rd | 1.887m | 67.012us | 5 | 5 | 100.00 |
| V2 | rma_hw_if | flash_ctrl_hw_rma | 33.253m | 95.679ms | 3 | 3 | 100.00 |
| flash_ctrl_hw_rma_reset | 18.135m | 420.250ms | 20 | 20 | 100.00 | ||
| flash_ctrl_lcmgr_intg | 13.640s | 47.259us | 20 | 20 | 100.00 | ||
| V2 | host_controller_arb | flash_ctrl_host_ctrl_arb | 40.471m | 1.487s | 5 | 5 | 100.00 |
| V2 | erase_suspend | flash_ctrl_erase_suspend | 9.451m | 3.353ms | 5 | 5 | 100.00 |
| V2 | program_reset | flash_ctrl_prog_reset | 3.920m | 2.668ms | 30 | 30 | 100.00 |
| V2 | full_memory_access | flash_ctrl_full_mem_access | 1.215h | 203.465ms | 5 | 5 | 100.00 |
| V2 | rd_buff_eviction | flash_ctrl_rd_buff_evict | 2.502m | 1.466ms | 5 | 5 | 100.00 |
| V2 | rd_buff_eviction_w_ecc | flash_ctrl_rw_evict | 32.100s | 34.671us | 30 | 40 | 75.00 |
| flash_ctrl_rw_evict_all_en | 32.240s | 130.053us | 36 | 40 | 90.00 | ||
| flash_ctrl_re_evict | 37.870s | 94.352us | 20 | 20 | 100.00 | ||
| V2 | host_arb | flash_ctrl_phy_arb | 10.603m | 40.911ms | 20 | 20 | 100.00 |
| V2 | host_interleave | flash_ctrl_phy_arb | 10.603m | 40.911ms | 20 | 20 | 100.00 |
| V2 | memory_protection | flash_ctrl_mp_regions | 17.584m | 16.978ms | 20 | 20 | 100.00 |
| V2 | fetch_code | flash_ctrl_fetch_code | 29.870s | 2.235ms | 10 | 10 | 100.00 |
| V2 | all_partitions | flash_ctrl_rand_ops | 17.878m | 222.867us | 20 | 20 | 100.00 |
| V2 | error_mp | flash_ctrl_error_mp | 43.246m | 43.601ms | 10 | 10 | 100.00 |
| V2 | error_prog_win | flash_ctrl_error_prog_win | 18.120m | 3.664ms | 10 | 10 | 100.00 |
| V2 | error_prog_type | flash_ctrl_error_prog_type | 44.377m | 1.737ms | 5 | 5 | 100.00 |
| V2 | error_read_seed | flash_ctrl_hw_read_seed_err | 14.180s | 48.553us | 20 | 20 | 100.00 |
| V2 | read_write_overflow | flash_ctrl_oversize_error | 3.733m | 6.740ms | 5 | 5 | 100.00 |
| V2 | flash_ctrl_disable | flash_ctrl_disable | 22.330s | 36.781us | 50 | 50 | 100.00 |
| V2 | flash_ctrl_connect | flash_ctrl_connect | 16.610s | 51.539us | 80 | 80 | 100.00 |
| V2 | stress_all | flash_ctrl_stress_all | 27.982m | 710.564us | 5 | 5 | 100.00 |
| V2 | secret_partition | flash_ctrl_hw_sec_otp | 4.851m | 3.361ms | 50 | 50 | 100.00 |
| flash_ctrl_otp_reset | 2.267m | 156.488us | 80 | 80 | 100.00 | ||
| V2 | isolation_partition | flash_ctrl_hw_rma | 33.253m | 95.679ms | 3 | 3 | 100.00 |
| V2 | interrupts | flash_ctrl_intr_rd | 4.381m | 1.537ms | 37 | 40 | 92.50 |
| flash_ctrl_intr_wr | 1.545m | 15.106ms | 9 | 10 | 90.00 | ||
| flash_ctrl_intr_rd_slow_flash | 6.020m | 170.444ms | 40 | 40 | 100.00 | ||
| flash_ctrl_intr_wr_slow_flash | 4.534m | 80.126ms | 9 | 10 | 90.00 | ||
| V2 | invalid_op | flash_ctrl_invalid_op | 1.601m | 2.041ms | 20 | 20 | 100.00 |
| V2 | mid_op_rst | flash_ctrl_mid_op_rst | 1.304m | 2.583ms | 5 | 5 | 100.00 |
| V2 | double_bit_err | flash_ctrl_read_word_sweep_derr | 22.710s | 19.579us | 2 | 5 | 40.00 |
| flash_ctrl_ro_derr | 3.477m | 4.680ms | 10 | 10 | 100.00 | ||
| flash_ctrl_rw_derr | 12.660m | 17.400ms | 7 | 10 | 70.00 | ||
| flash_ctrl_derr_detect | 1.763m | 122.352us | 5 | 5 | 100.00 | ||
| flash_ctrl_integrity | 13.208m | 15.970ms | 3 | 5 | 60.00 | ||
| V2 | single_bit_err | flash_ctrl_read_word_sweep_serr | 22.980s | 46.570us | 4 | 5 | 80.00 |
| flash_ctrl_ro_serr | 3.181m | 748.398us | 10 | 10 | 100.00 | ||
| flash_ctrl_rw_serr | 11.421m | 18.550ms | 6 | 10 | 60.00 | ||
| V2 | singlebit_err_counter | flash_ctrl_serr_counter | 1.735m | 2.481ms | 4 | 5 | 80.00 |
| V2 | singlebit_err_address | flash_ctrl_serr_address | 1.794m | 986.230us | 4 | 5 | 80.00 |
| V2 | scramble | flash_ctrl_wo | 4.323m | 11.257ms | 19 | 20 | 95.00 |
| flash_ctrl_write_word_sweep | 15.190s | 178.923us | 1 | 1 | 100.00 | ||
| flash_ctrl_read_word_sweep | 14.190s | 22.906us | 1 | 1 | 100.00 | ||
| flash_ctrl_ro | 2.773m | 913.215us | 19 | 20 | 95.00 | ||
| flash_ctrl_rw | 12.152m | 7.383ms | 20 | 20 | 100.00 | ||
| V2 | filesystem_support | flash_ctrl_fs_sup | 47.360s | 3.453ms | 5 | 5 | 100.00 |
| V2 | rma_write_process_error | flash_ctrl_rma_err | 17.363m | 157.544ms | 3 | 3 | 100.00 |
| flash_ctrl_hw_prog_rma_wipe_err | 5.511m | 10.013ms | 20 | 20 | 100.00 | ||
| V2 | alert_test | flash_ctrl_alert_test | 14.500s | 47.552us | 50 | 50 | 100.00 |
| V2 | intr_test | flash_ctrl_intr_test | 14.610s | 17.703us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | flash_ctrl_tl_errors | 21.990s | 579.206us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | flash_ctrl_tl_errors | 21.990s | 579.206us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | flash_ctrl_csr_hw_reset | 45.310s | 45.451us | 5 | 5 | 100.00 |
| flash_ctrl_csr_rw | 17.870s | 247.130us | 20 | 20 | 100.00 | ||
| flash_ctrl_csr_aliasing | 1.116m | 5.076ms | 5 | 5 | 100.00 | ||
| flash_ctrl_same_csr_outstanding | 36.070s | 1.248ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | flash_ctrl_csr_hw_reset | 45.310s | 45.451us | 5 | 5 | 100.00 |
| flash_ctrl_csr_rw | 17.870s | 247.130us | 20 | 20 | 100.00 | ||
| flash_ctrl_csr_aliasing | 1.116m | 5.076ms | 5 | 5 | 100.00 | ||
| flash_ctrl_same_csr_outstanding | 36.070s | 1.248ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 977 | 1013 | 96.45 | |||
| V2S | shadow_reg_update_error | flash_ctrl_shadow_reg_errors | 16.570s | 21.270us | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | flash_ctrl_shadow_reg_errors | 16.570s | 21.270us | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | flash_ctrl_shadow_reg_errors | 16.570s | 21.270us | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | flash_ctrl_shadow_reg_errors | 16.570s | 21.270us | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | flash_ctrl_shadow_reg_errors_with_csr_rw | 16.220s | 17.334us | 20 | 20 | 100.00 |
| V2S | tl_intg_err | flash_ctrl_sec_cm | 1.743h | 2.177ms | 2 | 5 | 40.00 |
| flash_ctrl_tl_intg_err | 15.191m | 349.082us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_reg_bus_integrity | flash_ctrl_tl_intg_err | 15.191m | 349.082us | 20 | 20 | 100.00 |
| V2S | sec_cm_host_bus_integrity | flash_ctrl_tl_intg_err | 15.191m | 349.082us | 20 | 20 | 100.00 |
| V2S | sec_cm_mem_bus_integrity | flash_ctrl_rd_intg | 32.820s | 66.569us | 3 | 3 | 100.00 |
| flash_ctrl_wr_intg | 15.350s | 44.503us | 3 | 3 | 100.00 | ||
| V2S | sec_cm_scramble_key_sideload | flash_ctrl_smoke | 4.865m | 5.246ms | 50 | 50 | 100.00 |
| V2S | sec_cm_lc_ctrl_intersig_mubi | flash_ctrl_otp_reset | 2.267m | 156.488us | 80 | 80 | 100.00 |
| flash_ctrl_disable | 22.330s | 36.781us | 50 | 50 | 100.00 | ||
| flash_ctrl_sec_info_access | 1.555m | 20.149ms | 50 | 50 | 100.00 | ||
| flash_ctrl_connect | 16.610s | 51.539us | 80 | 80 | 100.00 | ||
| V2S | sec_cm_ctrl_config_regwen | flash_ctrl_config_regwen | 14.440s | 124.015us | 5 | 5 | 100.00 |
| V2S | sec_cm_data_regions_config_regwen | flash_ctrl_csr_rw | 17.870s | 247.130us | 20 | 20 | 100.00 |
| V2S | sec_cm_data_regions_config_shadow | flash_ctrl_shadow_reg_errors | 16.570s | 21.270us | 20 | 20 | 100.00 |
| V2S | sec_cm_info_regions_config_regwen | flash_ctrl_csr_rw | 17.870s | 247.130us | 20 | 20 | 100.00 |
| V2S | sec_cm_info_regions_config_shadow | flash_ctrl_shadow_reg_errors | 16.570s | 21.270us | 20 | 20 | 100.00 |
| V2S | sec_cm_bank_config_regwen | flash_ctrl_csr_rw | 17.870s | 247.130us | 20 | 20 | 100.00 |
| V2S | sec_cm_bank_config_shadow | flash_ctrl_shadow_reg_errors | 16.570s | 21.270us | 20 | 20 | 100.00 |
| V2S | sec_cm_mem_ctrl_global_esc | flash_ctrl_disable | 22.330s | 36.781us | 50 | 50 | 100.00 |
| V2S | sec_cm_mem_ctrl_local_esc | flash_ctrl_rd_intg | 32.820s | 66.569us | 3 | 3 | 100.00 |
| flash_ctrl_access_after_disable | 14.060s | 24.253us | 3 | 3 | 100.00 | ||
| V2S | sec_cm_mem_disable_config_mubi | flash_ctrl_disable | 22.330s | 36.781us | 50 | 50 | 100.00 |
| V2S | sec_cm_exec_config_redun | flash_ctrl_fetch_code | 29.870s | 2.235ms | 10 | 10 | 100.00 |
| V2S | sec_cm_mem_scramble | flash_ctrl_rw | 12.152m | 7.383ms | 20 | 20 | 100.00 |
| V2S | sec_cm_mem_integrity | flash_ctrl_rw_serr | 11.421m | 18.550ms | 6 | 10 | 60.00 |
| flash_ctrl_rw_derr | 12.660m | 17.400ms | 7 | 10 | 70.00 | ||
| flash_ctrl_integrity | 13.208m | 15.970ms | 3 | 5 | 60.00 | ||
| V2S | sec_cm_rma_entry_mem_sec_wipe | flash_ctrl_hw_rma | 33.253m | 95.679ms | 3 | 3 | 100.00 |
| V2S | sec_cm_ctrl_fsm_sparse | flash_ctrl_sec_cm | 1.743h | 2.177ms | 2 | 5 | 40.00 |
| V2S | sec_cm_phy_fsm_sparse | flash_ctrl_sec_cm | 1.743h | 2.177ms | 2 | 5 | 40.00 |
| V2S | sec_cm_phy_prog_fsm_sparse | flash_ctrl_sec_cm | 1.743h | 2.177ms | 2 | 5 | 40.00 |
| V2S | sec_cm_ctr_redun | flash_ctrl_sec_cm | 1.743h | 2.177ms | 2 | 5 | 40.00 |
| V2S | sec_cm_phy_arbiter_ctrl_redun | flash_ctrl_phy_arb_redun | 22.880s | 856.036us | 4 | 5 | 80.00 |
| V2S | sec_cm_phy_host_grant_ctrl_consistency | flash_ctrl_phy_host_grant_err | 14.690s | 24.662us | 5 | 5 | 100.00 |
| V2S | sec_cm_phy_ack_ctrl_consistency | flash_ctrl_phy_ack_consistency | 14.280s | 24.185us | 5 | 5 | 100.00 |
| V2S | sec_cm_fifo_ctr_redun | flash_ctrl_sec_cm | 1.743h | 2.177ms | 2 | 5 | 40.00 |
| V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | flash_ctrl_sec_cm | 1.743h | 2.177ms | 2 | 5 | 40.00 |
| V2S | sec_cm_prog_tl_lc_gate_fsm_sparse | flash_ctrl_sec_cm | 1.743h | 2.177ms | 2 | 5 | 40.00 |
| V2S | TOTAL | 140 | 144 | 97.22 | |||
| V3 | asymmetric_read_path | flash_ctrl_rd_ooo | 43.870s | 147.795us | 1 | 1 | 100.00 |
| V3 | stress_all_with_rand_reset | flash_ctrl_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 1 | 1 | 100.00 | |||
| TOTAL | 1238 | 1278 | 96.87 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 9 | 9 | 9 | 100.00 |
| V2 | 55 | 55 | 41 | 74.55 |
| V2S | 12 | 12 | 10 | 83.33 |
| V3 | 2 | 1 | 1 | 50.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 96.29 | 95.74 | 93.96 | 97.54 | 92.52 | 98.23 | 98.06 | 98.00 |
UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 13 failures:
2.flash_ctrl_rw_evict.90854549110443899428470021077768219493808653281919028783054583947593157799198
Line 287, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rw_evict/latest/run.log
UVM_FATAL @ 21316.2 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00002530
UVM_INFO @ 21316.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.flash_ctrl_rw_evict.98177135072691585662502168731946677799663137808720292850300290093647146625403
Line 294, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/11.flash_ctrl_rw_evict/latest/run.log
UVM_FATAL @ 34576.4 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x000803a8
UVM_INFO @ 34576.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
15.flash_ctrl_rw_evict_all_en.84177526842869306647442599298137081352164754254408097945515121012573814379837
Line 291, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/15.flash_ctrl_rw_evict_all_en/latest/run.log
UVM_FATAL @ 93976.1 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00002fd0
UVM_INFO @ 93976.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
16.flash_ctrl_rw_evict_all_en.24982746657283963345732342179821126735252191584229756394717732795571074760607
Line 290, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/16.flash_ctrl_rw_evict_all_en/latest/run.log
UVM_FATAL @ 73661.0 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00041780
UVM_INFO @ 73661.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 6 failures:
Test flash_ctrl_integrity has 2 failures.
1.flash_ctrl_integrity.68210095776022170744496800097458165884118822433989229049681719583845528825309
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_integrity/latest/run.log
UVM_ERROR @ 4028844.9 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (892950181002482156545 [0x30682c5291a5b60401] vs 81715569080637214728 [0x46e08052196465008])
UVM_INFO @ 4028844.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.flash_ctrl_integrity.24259324596825522310861556731579328874212003268949644108386274536866491110953
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_integrity/latest/run.log
UVM_ERROR @ 743994.9 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (1257909478498030912640 [0x443100360100010480] vs 8344864170557428467392 [0x1c460411623004006c0])
UVM_INFO @ 743994.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test flash_ctrl_rw_serr has 3 failures.
3.flash_ctrl_rw_serr.34980687899240948895234148533253487565761074851036541692139537120128102519836
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_rw_serr/latest/run.log
UVM_ERROR @ 3393447.2 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (1551835935147086709504 [0x54200cc109803a0300] vs 1552988856651693556480 [0x54300cc109803a0300])
UVM_INFO @ 3393447.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.flash_ctrl_rw_serr.89015555282578630296553120523305348741093074336792164968167859099326168610377
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_rw_serr/latest/run.log
UVM_ERROR @ 3516802.7 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (17899762864228963560518 [0x3ca591c60021005ac46] vs 17899762864228963560534 [0x3ca591c60021005ac56])
UVM_INFO @ 3516802.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test flash_ctrl_rw_derr has 1 failures.
3.flash_ctrl_rw_derr.4611565431836431446183050763649225244338206535665026872202367330877124211003
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_rw_derr/latest/run.log
UVM_ERROR @ 10481102.4 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (39771491552385319961129 [0x86c04521080500a0229] vs 39771491693122808316457 [0x86c04529080500a0229])
UVM_INFO @ 10481102.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:289) m_otf_scb [process_read] unexpected double bit error * has 5 failures:
0.flash_ctrl_read_word_sweep_derr.42033473094911876137349805256208960584853576046694791411777886992094855241339
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_read_word_sweep_derr/latest/run.log
UVM_ERROR @ 23324.5 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x000155f0
UVM_INFO @ 23324.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.flash_ctrl_read_word_sweep_derr.110652419971131930500607509094493698853848204885742178346753341443964624675230
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_read_word_sweep_derr/latest/run.log
UVM_ERROR @ 25019.1 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x0009a6e0
UVM_INFO @ 25019.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
4.flash_ctrl_rw_derr.51272774659079014072249430790045726220356274160160793832135129329297530849323
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw_derr/latest/run.log
UVM_ERROR @ 15382990.6 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00003400
UVM_INFO @ 15382990.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.flash_ctrl_rw_derr.72722100402574207617725456026454499478362622110880439659733668432918622605657
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_rw_derr/latest/run.log
UVM_ERROR @ 1007713.0 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00003a80
UVM_INFO @ 1007713.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 5 failures:
Test flash_ctrl_intr_wr_slow_flash has 1 failures.
0.flash_ctrl_intr_wr_slow_flash.9795677484762174085223611745477339642386069869344692000541762781137659309462
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_intr_wr_slow_flash/latest/run.log
Job ID: smart:c995c064-7f40-4406-afa1-e18f9984077a
Test flash_ctrl_intr_wr has 1 failures.
3.flash_ctrl_intr_wr.85558384247833006873638972990599604796957916678228559148137013697397217903917
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_intr_wr/latest/run.log
Job ID: smart:58537d37-b947-455c-a539-3f60b0eff211
Test flash_ctrl_serr_counter has 1 failures.
4.flash_ctrl_serr_counter.84825195340221653166359538631648451410058059748080983133560851000279209600145
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_serr_counter/latest/run.log
Job ID: smart:e74819fc-c5b6-46fc-9a8c-20fb503feb5b
Test flash_ctrl_wo has 1 failures.
7.flash_ctrl_wo.108643040809143363937062208188418859562677767134173688578224014533855917089259
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_wo/latest/run.log
Job ID: smart:68042801-b401-48db-b6c5-0a9bf36b2ea8
Test flash_ctrl_rw_serr has 1 failures.
9.flash_ctrl_rw_serr.72612209185722325875703685627110325878684314246964002719716060292934301899480
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_rw_serr/latest/run.log
Job ID: smart:d12ba690-acfe-4519-aefc-03472ef61e0d
UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 2 failures:
Test flash_ctrl_serr_address has 1 failures.
4.flash_ctrl_serr_address.34517786108175922081279423774270817042502687163424506248071302907501376425706
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_serr_address/latest/run.log
UVM_ERROR @ 166028.5 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
UVM_INFO @ 166028.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test flash_ctrl_ro has 1 failures.
5.flash_ctrl_ro.93753297905235702331471513308614496725312781106394643859473531402221047813694
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_ro/latest/run.log
UVM_ERROR @ 227263.1 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
UVM_INFO @ 227263.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$isunknown(rdata_o))' has 1 failures:
0.flash_ctrl_sec_cm.90033217852543174204760149029049944461966398977265646740226915741552154365410
Line 379, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_sec_cm/latest/run.log
Offending '(!$isunknown(rdata_o))'
UVM_ERROR @ 84838.5 ns: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 84838.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_otf_item.sv:247) [rd_scr] ecc error is detected has 1 failures:
2.flash_ctrl_read_word_sweep_serr.113345102729137332940045091953412448062215425327480390199170025285929335761280
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_read_word_sweep_serr/latest/run.log
UVM_ERROR @ 5432.1 ns: (flash_otf_item.sv:247) [rd_scr] ecc error is detected
UVM_INFO @ 5432.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$isunknown(mem_tl_o.d_valid))' has 1 failures:
2.flash_ctrl_sec_cm.43183393094237321602347816351393149460574722778911576876242811785047802511907
Line 464, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_sec_cm/latest/run.log
Offending '(!$isunknown(mem_tl_o.d_valid))'
UVM_ERROR @ 130807.9 ns: (flash_ctrl.sv:1378) [ASSERT FAILED] MemTlDValidKnownO_A
UVM_INFO @ 130807.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_common_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 1 failures:
4.flash_ctrl_sec_cm.103536347475969006779057512866763697757105300697975911283337237246957511126052
Line 5935, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_sec_cm/latest/run.log
UVM_FATAL @ 1309357.2 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_common_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x000ffa18
UVM_INFO @ 1309357.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (*) != exp (*) has 1 failures:
4.flash_ctrl_phy_arb_redun.72550145163418535654018789952184647374173566123268766860722031305151607306815
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_phy_arb_redun/latest/run.log
UVM_ERROR @ 9473.0 ns: (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (0x2a) != exp (0x1a)
UVM_INFO @ 9473.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *a0b_3221e66a:ffffffff_3221e66a mismatch!! has 1 failures:
13.flash_ctrl_intr_rd.83577155885879852475110187336705635926637243749189052549658922256808656486929
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_intr_rd/latest/run.log
UVM_ERROR @ 10501294.6 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] 0: obs:exp 48154a0b_3221e66a:ffffffff_3221e66a mismatch!!
UVM_INFO @ 10501294.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *ad8df_79e97dfb:ffffffff_79e97dfb mismatch!! has 1 failures:
17.flash_ctrl_intr_rd.37071891194167241116533421964011324403635907199540784082266594045983337610233
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/17.flash_ctrl_intr_rd/latest/run.log
UVM_ERROR @ 817604.6 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] 7: obs:exp 948ad8df_79e97dfb:ffffffff_79e97dfb mismatch!!
UVM_INFO @ 817604.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *cce2ae1_20bdac01:ffffffff_20bdac* mismatch!! has 1 failures:
28.flash_ctrl_intr_rd.75236558608795233348919476157575943909379992531164285291893425484988216696154
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/28.flash_ctrl_intr_rd/latest/run.log
UVM_ERROR @ 1925494.7 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] 6: obs:exp 2cce2ae1_20bdac01:ffffffff_20bdac01 mismatch!!
UVM_INFO @ 1925494.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 1 failures:
29.flash_ctrl_rw_evict.52200496539653882569656564120649379170024065535913665067450769759835552636219
Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/29.flash_ctrl_rw_evict/latest/run.log
UVM_ERROR @ 40290.5 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
UVM_INFO @ 40290.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---