FLASH_CTRL Simulation Results

Thursday June 13 2024 19:02:12 UTC

GitHub Revision: `548a3880d8`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 95435389850697596633112362018639443702533575559488568730544091582583938649085

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.244m	83.479us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.700s	52.313us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	46.020s	191.778us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.970s	213.227us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.290m	2.235ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.129m	5.088ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	20.000s	240.394us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.970s	213.227us	20	20	100.00
		flash_ctrl_csr_aliasing	1.129m	5.088ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.470s	25.074us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.580s	35.969us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	27.210s	70.786us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	1.904m	416.269us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	35.751m	209.106ms	3	3	100.00
		flash_ctrl_hw_rma_reset	20.097m	540.455ms	20	20	100.00
		flash_ctrl_lcmgr_intg	14.280s	15.352us	19	20	95.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	53.294m	282.897ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	9.087m	4.169ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	3.360m	2.374ms	29	30	96.67
V2	full_memory_access	flash_ctrl_full_mem_access	1.236h	97.826ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.466m	3.179ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	31.990s	30.934us	29	40	72.50
		flash_ctrl_rw_evict_all_en	32.330s	42.297us	37	40	92.50
		flash_ctrl_re_evict	38.100s	124.413us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	8.486m	1.414ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	8.486m	1.414ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	15.131m	27.565ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	27.970s	1.386ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	31.096m	876.460us	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	46.240m	7.000ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	17.968m	14.681ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	48.445m	1.110ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	13.980s	33.615us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	4.181m	3.902ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.570s	19.188us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.320s	13.007us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	17.588m	855.462us	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.416m	12.770ms	50	50	100.00
		flash_ctrl_otp_reset	2.286m	67.513us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	35.751m	209.106ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	4.673m	20.726ms	38	40	95.00
		flash_ctrl_intr_wr	1.364m	10.876ms	9	10	90.00
		flash_ctrl_intr_rd_slow_flash	6.173m	195.573ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	4.740m	174.292ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.766m	16.033ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.285m	2.140ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	23.100s	22.422us	4	5	80.00
		flash_ctrl_ro_derr	2.893m	5.644ms	10	10	100.00
		flash_ctrl_rw_derr	11.954m	12.611ms	5	10	50.00
		flash_ctrl_derr_detect	1.770m	126.032us	5	5	100.00
		flash_ctrl_integrity	12.827m	15.941ms	3	5	60.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	23.340s	25.910us	5	5	100.00
		flash_ctrl_ro_serr	2.716m	3.481ms	10	10	100.00
		flash_ctrl_rw_serr	14.248m	8.380ms	8	10	80.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.505m	3.518ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.770m	14.060ms	5	5	100.00
V2	scramble	flash_ctrl_wo	4.270m	3.140ms	20	20	100.00
		flash_ctrl_write_word_sweep	15.000s	269.273us	1	1	100.00
		flash_ctrl_read_word_sweep	14.530s	25.289us	1	1	100.00
		flash_ctrl_ro	2.560m	2.301ms	20	20	100.00
		flash_ctrl_rw	12.945m	16.511ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	46.210s	4.668ms	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	25.909m	93.489ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.563m	10.012ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.450s	220.499us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	13.840s	133.882us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	20.710s	566.392us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	20.710s	566.392us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	46.020s	191.778us	5	5	100.00
		flash_ctrl_csr_rw	17.970s	213.227us	20	20	100.00
		flash_ctrl_csr_aliasing	1.129m	5.088ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.120s	846.969us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	46.020s	191.778us	5	5	100.00
		flash_ctrl_csr_rw	17.970s	213.227us	20	20	100.00
		flash_ctrl_csr_aliasing	1.129m	5.088ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.120s	846.969us	20	20	100.00
V2		TOTAL			984	1013	97.14
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.330s	18.323us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.330s	18.323us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.330s	18.323us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.330s	18.323us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.320s	14.467us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.389h	1.160ms	5	5	100.00
		flash_ctrl_tl_intg_err	14.933m	339.671us	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	14.933m	339.671us	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	14.933m	339.671us	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	33.560s	116.335us	3	3	100.00
		flash_ctrl_wr_intg	15.460s	44.434us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.244m	83.479us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.286m	67.513us	80	80	100.00
		flash_ctrl_disable	22.570s	19.188us	50	50	100.00
		flash_ctrl_sec_info_access	1.447m	13.315ms	50	50	100.00
		flash_ctrl_connect	16.320s	13.007us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.170s	72.402us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.970s	213.227us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.330s	18.323us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.970s	213.227us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.330s	18.323us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.970s	213.227us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.330s	18.323us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.570s	19.188us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	33.560s	116.335us	3	3	100.00
		flash_ctrl_access_after_disable	13.820s	42.068us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.570s	19.188us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	27.970s	1.386ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	12.945m	16.511ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	14.248m	8.380ms	8	10	80.00
		flash_ctrl_rw_derr	11.954m	12.611ms	5	10	50.00
		flash_ctrl_integrity	12.827m	15.941ms	3	5	60.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	35.751m	209.106ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.389h	1.160ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.389h	1.160ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.389h	1.160ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.389h	1.160ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	22.770s	785.649us	4	5	80.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.530s	28.767us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.430s	27.924us	4	5	80.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.389h	1.160ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.389h	1.160ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.389h	1.160ms	5	5	100.00
V2S		TOTAL			142	144	98.61
V3	asymmetric_read_path	flash_ctrl_rd_ooo	48.070s	156.647us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1247	1278	97.57

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	45	81.82
V2S	12	12	10	83.33
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.26	95.74	93.89	98.31	92.52	98.27	97.09	98.03

Failure Buckets

UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 13 failures:

Test flash_ctrl_rw_evict has 10 failures.

2.flash_ctrl_rw_evict.111794109364731237261103481929378820996488839302357550232135367925811022152264
Line 286, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rw_evict/latest/run.log

  UVM_FATAL @ 18013.3 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00084e50
  UVM_INFO @ 18013.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.flash_ctrl_rw_evict.37060363647480302308675520712002249114998428575283686245182111343566513604910
Line 291, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_rw_evict/latest/run.log

  UVM_FATAL @ 12550.4 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00003e58
  UVM_INFO @ 12550.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test flash_ctrl_rw_evict_all_en has 3 failures.

8.flash_ctrl_rw_evict_all_en.106034045476965123551151307856896115763742676315837456351228573277125204637325
Line 295, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_FATAL @ 41092.0 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00050148
  UVM_INFO @ 41092.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

22.flash_ctrl_rw_evict_all_en.28794167976521861193344755482032677724088769395607136561897335460006781364092
Line 298, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/22.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_FATAL @ 50098.9 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00043678
  UVM_INFO @ 50098.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 5 failures:
- Test flash_ctrl_rw_serr has 1 failures.
  - 1.flash_ctrl_rw_serr.76070475318532168641020314082852152711818247490562694020967316639233878531812
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_serr/latest/run.log
```
  Job ID: smart:4e5e4697-99a3-4449-ae80-adfa4d622c90
```
- Test flash_ctrl_intr_wr has 1 failures.
  - 3.flash_ctrl_intr_wr.112510576898281953445528518143960898550141255149583446260324231107733222915639
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_intr_wr/latest/run.log
```
  Job ID: smart:3fc68cf4-5837-459c-a3e6-b81b8b03f96e
```
- Test flash_ctrl_integrity has 1 failures.
  - 4.flash_ctrl_integrity.93260467932854351902537288382149082105617814059825080573348193968212212158508
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_integrity/latest/run.log
```
  Job ID: smart:7baa67fb-55a6-4455-a7b4-137a1eebda21
```
- Test flash_ctrl_rw_derr has 1 failures.
  - 8.flash_ctrl_rw_derr.24968595923068032774070009685634795228267532243198899630628535037705671261923
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_rw_derr/latest/run.log
```
  Job ID: smart:41df9e8d-d25f-43fb-a67d-4ec9a55febfc
```
- Test flash_ctrl_prog_reset has 1 failures.
  - 16.flash_ctrl_prog_reset.2624106584108009293967238126539296018819887209299718786059528757308318903385
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/16.flash_ctrl_prog_reset/latest/run.log
```
  Job ID: smart:340865f3-c0a4-4043-bec5-1e8ee1d12702
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:289) m_otf_scb [process_read] unexpected double bit error * has 4 failures:
- Test flash_ctrl_read_word_sweep_derr has 1 failures.
  - 0.flash_ctrl_read_word_sweep_derr.45391727524841678887903548519186253986139241296654944275111387985867304708810
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_read_word_sweep_derr/latest/run.log
```
  UVM_ERROR @ 21057.0 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x000157f0
  UVM_INFO @ 21057.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_integrity has 1 failures.
  - 2.flash_ctrl_integrity.13883577987184436561107307706480793236471061444140447661166444523567166223340
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_integrity/latest/run.log
```
  UVM_ERROR @ 1890444.7 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00002200
  UVM_INFO @ 1890444.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_rw_derr has 2 failures.
  - 4.flash_ctrl_rw_derr.56875072316512084251325413924280494381635482591534971539630010620485598085004
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 23915749.2 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00004c00
  UVM_INFO @ 23915749.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.flash_ctrl_rw_derr.57691180511536669509541439751825549469672119273115154730986711996479180674051
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 3462600.0 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00003498
  UVM_INFO @ 3462600.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (*) != exp (*) has 2 failures:
- Test flash_ctrl_phy_arb_redun has 1 failures.
  - 2.flash_ctrl_phy_arb_redun.25794626953219995222326652656924086152978118249748416549278157211806322434572
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_phy_arb_redun/latest/run.log
```
  UVM_ERROR @ 11807.4 ns: (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (0x2a) != exp (0x40)
  UVM_INFO @ 11807.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_phy_ack_consistency has 1 failures.
  - 4.flash_ctrl_phy_ack_consistency.58036261213957386706154496677324567271026162247919098383447938281505954368780
    Line 284, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_phy_ack_consistency/latest/run.log
```
  UVM_ERROR @ 43093.7 ns: (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (0x2a) != exp (0x79)
  UVM_INFO @ 43093.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 1 failures:
- Test flash_ctrl_rw_serr has 1 failures.
  - 0.flash_ctrl_rw_serr.69068512416504031569062795847607309501704252226316013548376186224194602193948
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_serr/latest/run.log
```
  UVM_ERROR @ 619566.8 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 619566.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 1 failures:
- Test flash_ctrl_rw_derr has 1 failures.
  - 1.flash_ctrl_rw_derr.112577302145532986648229807672265642278042166329745297357082892265817574495460
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 24869351.5 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (56688004497585623607552 [0xc01101900a251312900] vs 56688076555179661535488 [0xc01111900a251312900])
  UVM_INFO @ 24869351.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 1 failures:
- Test flash_ctrl_rw_derr has 1 failures.
  - 7.flash_ctrl_rw_derr.115375773555406838527455853356897584776712461016747821433587092006919630377799
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 1687120.1 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (43867152864929366147074 [0x94a0b0a088432080002] vs 43867152867128389402626 [0x94a0b0a0a8432080002])
  UVM_INFO @ 1687120.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.std_fault_status.lcmgr_intg_err reset value: * has 1 failures:
- Test flash_ctrl_lcmgr_intg has 1 failures.
  - 7.flash_ctrl_lcmgr_intg.92268714882550069730188806928121232171965834956574937469247429277270812888131
    Line 285, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_lcmgr_intg/latest/run.log
```
  UVM_ERROR @ 13754.2 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.std_fault_status.lcmgr_intg_err reset value: 0x0
  UVM_INFO @ 13754.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *c191a_a78eb4a4:ffffffff_a78eb4a* mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 30.flash_ctrl_intr_rd.63936839022958914400059022161090482624466613752211665070247128012906207426805
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/30.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 424352.7 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    7: obs:exp    866c191a_a78eb4a4:ffffffff_a78eb4a4  mismatch!!
  UVM_INFO @ 424352.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp def8916a_6ea8751b:ffffffff_ffffffff mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 33.flash_ctrl_intr_rd.44118529917999988778088161839973533216028572670854045394323283932982925056302
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/33.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 2349022.4 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    7: obs:exp    def8916a_6ea8751b:ffffffff_ffffffff  mismatch!!
  UVM_INFO @ 2349022.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 1 failures:
- Test flash_ctrl_rw_evict has 1 failures.
  - 39.flash_ctrl_rw_evict.76646423751078251812154839715287949612137538039357009364221154265950761861834
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/39.flash_ctrl_rw_evict/latest/run.log
```
  UVM_ERROR @ 52869.5 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 52869.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```