FLASH_CTRL Simulation Results

Friday June 21 2024 23:02:45 UTC

GitHub Revision: `de38ce313c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 40294666978553523170681160506532247841705182588034413483474981853853670477454

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.906m	687.495us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.080s	23.405us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	46.760s	153.408us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.930s	92.938us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.424m	3.213ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.061m	1.306ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	19.860s	147.407us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.930s	92.938us	20	20	100.00
		flash_ctrl_csr_aliasing	1.061m	1.306ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	14.220s	25.295us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	14.000s	16.902us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.640s	79.761us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	1.858m	114.793us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	35.870m	271.813ms	3	3	100.00
		flash_ctrl_hw_rma_reset	15.414m	150.181ms	20	20	100.00
		flash_ctrl_lcmgr_intg	13.800s	25.163us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	51.660m	303.615ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	9.905m	4.006ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	3.672m	8.664ms	29	30	96.67
V2	full_memory_access	flash_ctrl_full_mem_access	1.164h	203.469ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.561m	1.404ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	31.910s	43.454us	40	40	100.00
		flash_ctrl_rw_evict_all_en	31.910s	27.424us	38	40	95.00
		flash_ctrl_re_evict	36.290s	319.280us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	10.376m	8.518ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	10.376m	8.518ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	9.230m	30.898ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	32.810s	2.712ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	15.351m	348.494us	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	41.969m	6.197ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	16.213m	2.869ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	50.327m	554.677us	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	13.830s	26.951us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	4.392m	1.836ms	4	5	80.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.520s	27.453us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.260s	24.901us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	24.963m	1.466ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.058m	5.993ms	50	50	100.00
		flash_ctrl_otp_reset	2.232m	86.921us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	35.870m	271.813ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	4.936m	3.767ms	38	40	95.00
		flash_ctrl_intr_wr	1.314m	9.680ms	8	10	80.00
		flash_ctrl_intr_rd_slow_flash	6.169m	12.374ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	4.879m	104.638ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.611m	3.900ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.248m	1.148ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	28.090s	429.314us	5	5	100.00
		flash_ctrl_ro_derr	3.111m	826.658us	10	10	100.00
		flash_ctrl_rw_derr	12.383m	3.956ms	7	10	70.00
		flash_ctrl_derr_detect	1.780m	354.658us	5	5	100.00
		flash_ctrl_integrity	11.634m	41.028ms	3	5	60.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	29.150s	158.397us	5	5	100.00
		flash_ctrl_ro_serr	2.660m	1.339ms	10	10	100.00
		flash_ctrl_rw_serr	11.354m	4.380ms	6	10	60.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.696m	1.023ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.954m	7.463ms	5	5	100.00
V2	scramble	flash_ctrl_wo	4.170m	3.719ms	20	20	100.00
		flash_ctrl_write_word_sweep	15.380s	144.010us	1	1	100.00
		flash_ctrl_read_word_sweep	18.250s	314.929us	1	1	100.00
		flash_ctrl_ro	2.383m	2.613ms	20	20	100.00
		flash_ctrl_rw	12.208m	8.228ms	19	20	95.00
V2	filesystem_support	flash_ctrl_fs_sup	42.870s	581.205us	4	5	80.00
V2	rma_write_process_error	flash_ctrl_rma_err	15.586m	42.145ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.375m	10.013ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.580s	283.039us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.370s	52.720us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	20.660s	88.796us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	20.660s	88.796us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	46.760s	153.408us	5	5	100.00
		flash_ctrl_csr_rw	17.930s	92.938us	20	20	100.00
		flash_ctrl_csr_aliasing	1.061m	1.306ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.640s	227.836us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	46.760s	153.408us	5	5	100.00
		flash_ctrl_csr_rw	17.930s	92.938us	20	20	100.00
		flash_ctrl_csr_aliasing	1.061m	1.306ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.640s	227.836us	20	20	100.00
V2		TOTAL			994	1013	98.12
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.470s	26.123us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.470s	26.123us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.470s	26.123us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.470s	26.123us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.630s	21.377us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.341h	988.235us	5	5	100.00
		flash_ctrl_tl_intg_err	15.645m	2.739ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.645m	2.739ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.645m	2.739ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	32.730s	65.400us	3	3	100.00
		flash_ctrl_wr_intg	15.240s	85.350us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.906m	687.495us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.232m	86.921us	80	80	100.00
		flash_ctrl_disable	22.520s	27.453us	50	50	100.00
		flash_ctrl_sec_info_access	1.511m	25.646ms	50	50	100.00
		flash_ctrl_connect	16.260s	24.901us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.350s	20.821us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.930s	92.938us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.470s	26.123us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.930s	92.938us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.470s	26.123us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.930s	92.938us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.470s	26.123us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.520s	27.453us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	32.730s	65.400us	3	3	100.00
		flash_ctrl_access_after_disable	13.830s	19.630us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.520s	27.453us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	32.810s	2.712ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	12.208m	8.228ms	19	20	95.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	11.354m	4.380ms	6	10	60.00
		flash_ctrl_rw_derr	12.383m	3.956ms	7	10	70.00
		flash_ctrl_integrity	11.634m	41.028ms	3	5	60.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	35.870m	271.813ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.341h	988.235us	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.341h	988.235us	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.341h	988.235us	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.341h	988.235us	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	17.640s	685.958us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.490s	15.421us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.280s	45.605us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.341h	988.235us	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.341h	988.235us	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.341h	988.235us	5	5	100.00
V2S		TOTAL			144	144	100.00
V3	asymmetric_read_path	flash_ctrl_rd_ooo	44.090s	319.142us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1259	1278	98.51

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	45	81.82
V2S	12	12	12	100.00
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.32	95.73	94.04	98.31	92.52	98.25	97.18	98.21

Failure Buckets

Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 6 failures:
- Test flash_ctrl_rw has 1 failures.
  - 0.flash_ctrl_rw.21729594305102327396315281602639998852508775400973714513370432721409592675321
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw/latest/run.log
```
  Job ID: smart:660cab7b-6251-43ea-b401-2a0115df9559
```
- Test flash_ctrl_rw_serr has 2 failures.
  - 0.flash_ctrl_rw_serr.69196136297523437318687627061767051891979036085617716614913389774448297990536
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_serr/latest/run.log
```
  Job ID: smart:897bedb2-6837-41c5-9adf-8d17155e80c9
```
  - 3.flash_ctrl_rw_serr.46904348817612615391829408940602625380227677481471310927638557136576079358158
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_rw_serr/latest/run.log
```
  Job ID: smart:757a9fd9-0137-44e4-93da-2202ae8ce0ec
```
- Test flash_ctrl_intr_wr has 2 failures.
  - 0.flash_ctrl_intr_wr.102123041434136776955014110501630276523772781605972091842979672659078258245252
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_intr_wr/latest/run.log
```
  Job ID: smart:d792d712-4f1b-4ed8-882e-a713ae654e16
```
  - 1.flash_ctrl_intr_wr.44092025001011971746767184124639832381133843060483464278812315250563246744903
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_intr_wr/latest/run.log
```
  Job ID: smart:bbf57e13-130b-4ce0-bcaa-97e606b12bb3
```
- Test flash_ctrl_prog_reset has 1 failures.
  - 11.flash_ctrl_prog_reset.51896547012636731590622470450839998055230508863729213678857596009400328406561
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/11.flash_ctrl_prog_reset/latest/run.log
```
  Job ID: smart:70619e99-84c3-4a3f-8800-08e439ea891a
```

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 4 failures:

Test flash_ctrl_rw_derr has 2 failures.

0.flash_ctrl_rw_derr.56070246868834856475774725822410449090900959942215694882963963271139782420872
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_derr/latest/run.log

  UVM_ERROR @ 2218007.2 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (18889764058105775915170 [0x40004232896800c00a2] vs 18889764058105775915138 [0x40004232896800c0082])
  UVM_INFO @ 2218007.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.flash_ctrl_rw_derr.2279304003564068542155525007883046692756827407735840657736392130847861744400
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw_derr/latest/run.log

  UVM_ERROR @ 1115386.0 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (10053764613115547804187 [0x2210403108030c8e21b] vs 10053764613115547805211 [0x2210403108030c8e61b])
  UVM_INFO @ 1115386.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_rw_serr has 2 failures.

2.flash_ctrl_rw_serr.67287533980222006494987581948749898820306790913908508236078236072284249243537
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 18258179.6 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (33210917321175080898824 [0x7085e1040a0a44c1108] vs 33210917321175080894728 [0x7085e1040a0a44c0108])
  UVM_INFO @ 18258179.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.flash_ctrl_rw_serr.4180092122364094383610946977855039035095512468894782879684330156945598063098
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 15586531.3 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (9448192426539720673290 [0x20030027944dc08880a] vs 9445886583530506979338 [0x20010027944dc08880a])
  UVM_INFO @ 15586531.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:289) m_otf_scb [process_read] unexpected double bit error * has 3 failures:
- Test flash_ctrl_rw_derr has 1 failures.
  - 1.flash_ctrl_rw_derr.76338430776206267634201141446755106360659530320336420969622514186952940553415
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 3383270.9 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00004400
  UVM_INFO @ 3383270.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_integrity has 2 failures.
  - 1.flash_ctrl_integrity.43419584634243730505104562753983722442730645072685721043065966572662757175180
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_integrity/latest/run.log
```
  UVM_ERROR @ 1864865.3 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00002628
  UVM_INFO @ 1864865.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.flash_ctrl_integrity.50546014289703368160776323831161567414098062765311491814731823446985022362078
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_integrity/latest/run.log
```
  UVM_ERROR @ 10296931.0 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00004a00
  UVM_INFO @ 10296931.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 2 failures:
- Test flash_ctrl_rw_evict_all_en has 2 failures.
  - 10.flash_ctrl_rw_evict_all_en.18241175694169532619860419225102254217953187384335860440198276163968297368243
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_rw_evict_all_en/latest/run.log
```
  UVM_ERROR @ 11216.4 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 11216.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 13.flash_ctrl_rw_evict_all_en.24391961897260510710970376750046188710428954384948127851998042714856129788228
    Line 291, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_rw_evict_all_en/latest/run.log
```
  UVM_ERROR @ 66742.1 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 66742.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_scoreboard.sv:481) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@315212) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test flash_ctrl_oversize_error has 1 failures.

2.flash_ctrl_oversize_error.23963323700153920522653589829791011458332009072544191727292334891965339000987
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_oversize_error/latest/run.log

  UVM_ERROR @ 451217.0 ns: (cip_base_scoreboard.sv:481) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@315212) { a_addr: 'hc0020  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hf9  a_opcode: 'h4  a_user: 'h2472a  d_param: 'h0  d_source: 'hf9  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h1  d_error: 'h1  d_sink: 'h0  d_user: 'heaa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 451217.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 1 failures:
- Test flash_ctrl_fs_sup has 1 failures.
  - 4.flash_ctrl_fs_sup.14138937882852608468399175731769986338688446054207883622299390259135357715191
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_fs_sup/latest/run.log
```
  UVM_ERROR @ 581205.1 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 581205.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp cb810acc_245d75b9:ffffffff_ffffffff mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 11.flash_ctrl_intr_rd.11623855006409424876614141683838937091203453393987250569681819324614448254727
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/11.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 246608.3 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    6: obs:exp    cb810acc_245d75b9:ffffffff_ffffffff  mismatch!!
  UVM_INFO @ 246608.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *bd68459_3fdb8827:ffffffff_3fdb* mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 25.flash_ctrl_intr_rd.85335495480277136556342862456931925324645217679317019348351700167601735144815
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/25.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 1174548.1 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    7: obs:exp    1bd68459_3fdb8827:ffffffff_3fdb8827  mismatch!!
  UVM_INFO @ 1174548.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```