FLASH_CTRL Simulation Results

Saturday June 22 2024 23:02:20 UTC

GitHub Revision: `8fdb25c8d9`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 116774179587740886356693500529232784059703555433764635649168222249757162669

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.632m	117.376us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.580s	42.450us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	47.140s	99.181us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.940s	122.126us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.429m	8.421ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.206m	9.182ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	19.610s	52.429us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.940s	122.126us	20	20	100.00
		flash_ctrl_csr_aliasing	1.206m	9.182ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.720s	15.494us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.850s	54.296us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.990s	82.261us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	1.875m	233.703us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	47.230m	794.960ms	3	3	100.00
		flash_ctrl_hw_rma_reset	17.649m	230.177ms	20	20	100.00
		flash_ctrl_lcmgr_intg	13.980s	21.023us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	44.484m	377.612ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	8.134m	2.810ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	3.559m	9.001ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.231h	195.648ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.258m	15.317ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	32.950s	156.615us	37	40	92.50
		flash_ctrl_rw_evict_all_en	32.760s	29.423us	37	40	92.50
		flash_ctrl_re_evict	36.060s	210.793us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	8.352m	1.498ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	8.352m	1.498ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	24.346m	53.805ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	28.410s	556.694us	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	20.368m	479.680us	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	46.389m	15.487ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	18.473m	425.735us	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	47.622m	2.605ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	14.390s	15.578us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	4.357m	5.161ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	23.380s	129.715us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.420s	19.030us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	35.281m	1.245ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.571m	3.121ms	50	50	100.00
		flash_ctrl_otp_reset	2.249m	178.471us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	47.230m	794.960ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	4.320m	3.812ms	38	40	95.00
		flash_ctrl_intr_wr	1.557m	28.149ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	7.036m	130.865ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	5.734m	127.479ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.655m	3.851ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.332m	11.651ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	28.420s	805.178us	5	5	100.00
		flash_ctrl_ro_derr	2.969m	2.769ms	10	10	100.00
		flash_ctrl_rw_derr	14.599m	15.917ms	5	10	50.00
		flash_ctrl_derr_detect	1.749m	335.111us	5	5	100.00
		flash_ctrl_integrity	13.886m	4.418ms	3	5	60.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	29.360s	1.265ms	5	5	100.00
		flash_ctrl_ro_serr	3.043m	2.819ms	10	10	100.00
		flash_ctrl_rw_serr	12.025m	14.738ms	7	10	70.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.570m	4.179ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.592m	813.482us	4	5	80.00
V2	scramble	flash_ctrl_wo	3.674m	2.517ms	19	20	95.00
		flash_ctrl_write_word_sweep	15.500s	663.056us	1	1	100.00
		flash_ctrl_read_word_sweep	18.760s	1.103ms	1	1	100.00
		flash_ctrl_ro	2.515m	670.049us	20	20	100.00
		flash_ctrl_rw	12.918m	16.628ms	17	20	85.00
V2	filesystem_support	flash_ctrl_fs_sup	44.600s	332.736us	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	16.247m	328.665ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	3.041m	10.021ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.680s	551.903us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.390s	49.025us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	20.270s	228.972us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	20.270s	228.972us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	47.140s	99.181us	5	5	100.00
		flash_ctrl_csr_rw	17.940s	122.126us	20	20	100.00
		flash_ctrl_csr_aliasing	1.206m	9.182ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	30.670s	325.604us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	47.140s	99.181us	5	5	100.00
		flash_ctrl_csr_rw	17.940s	122.126us	20	20	100.00
		flash_ctrl_csr_aliasing	1.206m	9.182ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	30.670s	325.604us	20	20	100.00
V2		TOTAL			990	1013	97.73
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.620s	37.731us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.620s	37.731us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.620s	37.731us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.620s	37.731us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.690s	22.623us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.373h	4.080ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.287m	2.756ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.287m	2.756ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.287m	2.756ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	31.840s	65.033us	3	3	100.00
		flash_ctrl_wr_intg	15.430s	95.584us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.632m	117.376us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.249m	178.471us	80	80	100.00
		flash_ctrl_disable	23.380s	129.715us	50	50	100.00
		flash_ctrl_sec_info_access	1.500m	4.961ms	50	50	100.00
		flash_ctrl_connect	16.420s	19.030us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.490s	77.011us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.940s	122.126us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.620s	37.731us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.940s	122.126us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.620s	37.731us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.940s	122.126us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.620s	37.731us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	23.380s	129.715us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	31.840s	65.033us	3	3	100.00
		flash_ctrl_access_after_disable	13.990s	24.222us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	23.380s	129.715us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	28.410s	556.694us	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	12.918m	16.628ms	17	20	85.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	12.025m	14.738ms	7	10	70.00
		flash_ctrl_rw_derr	14.599m	15.917ms	5	10	50.00
		flash_ctrl_integrity	13.886m	4.418ms	3	5	60.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	47.230m	794.960ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.373h	4.080ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.373h	4.080ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.373h	4.080ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.373h	4.080ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	21.220s	716.457us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.340s	24.156us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.800s	15.365us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.373h	4.080ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.373h	4.080ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.373h	4.080ms	5	5	100.00
V2S		TOTAL			144	144	100.00
V3	asymmetric_read_path	flash_ctrl_rd_ooo	48.630s	146.207us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1255	1278	98.20

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	46	83.64
V2S	12	12	12	100.00
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.20	95.73	93.98	98.31	91.84	98.29	97.09	98.15

Failure Buckets

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 6 failures:

Test flash_ctrl_rw_serr has 2 failures.

0.flash_ctrl_rw_serr.112667472169788318279699374712282736511605922766143670587376265411030954415288
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 445030.2 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (39052086064157059249096 [0x845049058880018f3c8] vs 39052086064122699510728 [0x845049058800018f3c8])
  UVM_INFO @ 445030.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.flash_ctrl_rw_serr.53270494874311208410843867946750771232012811323061419761223393957265102501505
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 3719301.6 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (9778072020462815218700 [0x2121202382a40310c0c] vs 9778072020462815218692 [0x2121202382a40310c04])
  UVM_INFO @ 3719301.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_serr_address has 1 failures.

0.flash_ctrl_serr_address.9162744566767886208580500646680623252042581755854090254398721535330459027423
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_serr_address/latest/run.log

  UVM_ERROR @ 2797545.8 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (51983214167259735918110 [0xb0204040a4009f0061e] vs 51983214167809491731998 [0xb0204040ac009f0061e])
  UVM_INFO @ 2797545.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_rw_derr has 3 failures.

1.flash_ctrl_rw_derr.93531410217311791961915559786376784645737922671402957484219198619573519392925
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_derr/latest/run.log

  UVM_ERROR @ 2197726.9 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (33056578890955206707200 [0x7000030001005484800] vs 33056578890886487230464 [0x7000030000005484800])
  UVM_INFO @ 2197726.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.flash_ctrl_rw_derr.1509622606878404130403341280254773352283190546635186696187142017904702369155
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_rw_derr/latest/run.log

  UVM_ERROR @ 7853902.8 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (28380901494257538434129 [0x6028820f4910d920451] vs 28380892487058283693137 [0x6028800f4910d920451])
  UVM_INFO @ 7853902.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 4 failures:

Test flash_ctrl_rw_evict has 2 failures.

2.flash_ctrl_rw_evict.100360672887059277048277682553450855530743903231136945028343294088355014707419
Line 288, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rw_evict/latest/run.log

  UVM_ERROR @ 17471.4 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 17471.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

30.flash_ctrl_rw_evict.66937249033416220133313210289561298022319075887069391726206509463142202713010
Line 291, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/30.flash_ctrl_rw_evict/latest/run.log

  UVM_ERROR @ 24408.2 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 24408.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_rw_evict_all_en has 2 failures.

13.flash_ctrl_rw_evict_all_en.113114970858768668173772168290538866091006576043544211922716345405331409969404
Line 291, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_ERROR @ 8936.7 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 8936.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

20.flash_ctrl_rw_evict_all_en.8694285665797333324592655957083800790315559868833002385238473601734046397246
Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/20.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_ERROR @ 33716.4 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 33716.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 3 failures:
- Test flash_ctrl_wo has 1 failures.
  - 5.flash_ctrl_wo.98323581266712673399566978664427536268470010612757825242708343221041150591737
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_wo/latest/run.log
```
  Job ID: smart:e99c2120-bc74-421d-b826-1ebeb53c6f8b
```
- Test flash_ctrl_rw has 1 failures.
  - 5.flash_ctrl_rw.70731342520251684614049357181237049076410719239176020613195720018179441161480
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_rw/latest/run.log
```
  Job ID: smart:598388b2-faae-4230-8859-b479dd52f4a5
```
- Test flash_ctrl_rw_derr has 1 failures.
  - 6.flash_ctrl_rw_derr.103093437850988229732296288345240512381389519799423710154274663747639994655050
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_rw_derr/latest/run.log
```
  Job ID: smart:df68fb35-4269-4265-99ac-04ecf36df3c8
```

UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 3 failures:

Test flash_ctrl_rw has 2 failures.

7.flash_ctrl_rw.7915169511879238076726796117558746673333953761930345192817359365848907983941
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_rw/latest/run.log

  UVM_ERROR @ 233700.5 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 233700.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

16.flash_ctrl_rw.37840986475169502366653029888655915046705709758803028716323228126943786316369
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/16.flash_ctrl_rw/latest/run.log

  UVM_ERROR @ 2333118.2 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 2333118.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_rw_serr has 1 failures.

7.flash_ctrl_rw_serr.115591918111936025407512938116990927414784168103827001153434951131167198421712
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 11263065.5 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 11263065.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:289) m_otf_scb [process_read] unexpected double bit error * has 2 failures:
- Test flash_ctrl_integrity has 2 failures.
  - 0.flash_ctrl_integrity.82872446295404207504320084021544415971811841324306363910480639085964556129456
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_integrity/latest/run.log
```
  UVM_ERROR @ 3597899.2 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00002608
  UVM_INFO @ 3597899.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.flash_ctrl_integrity.72854086260186577052238955357222744723654707318681661604864756296445222602893
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_integrity/latest/run.log
```
  UVM_ERROR @ 5348326.4 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00002200
  UVM_INFO @ 5348326.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 1 failures:
- Test flash_ctrl_rw_derr has 1 failures.
  - 4.flash_ctrl_rw_derr.92703038115205110364849267160469797401656408251866562586150596227608091474860
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 7175378.8 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (28341156967773796304965 [0x6006090084e20040845] vs 28341158093673703147589 [0x6006094084e20040845])
  UVM_INFO @ 7175378.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp de11b969_6507d556:ffffffff_ffffffff mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 13.flash_ctrl_intr_rd.2092940103722564082616776439684607701291778712916946454579674013505405542199
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 675697.5 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    4: obs:exp    de11b969_6507d556:ffffffff_ffffffff  mismatch!!
  UVM_INFO @ 675697.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: * has 1 failures:
- Test flash_ctrl_rw_evict has 1 failures.
  - 14.flash_ctrl_rw_evict.113106801548324871711024778664543675156202855236459010125968918804218447947594
    Line 291, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/14.flash_ctrl_rw_evict/latest/run.log
```
  UVM_ERROR @ 41771.3 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: 0x0
  UVM_INFO @ 41771.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *c55554_7da23776:ffffffff_7da* mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 19.flash_ctrl_intr_rd.26184184676486208378947669974867245462521940394823545995604874058091132892683
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/19.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 4781199.9 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    0: obs:exp    05c55554_7da23776:ffffffff_7da23776  mismatch!!
  UVM_INFO @ 4781199.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 1 failures:
- Test flash_ctrl_rw_evict_all_en has 1 failures.
  - 21.flash_ctrl_rw_evict_all_en.103580891360077973164105061807199799981694752116550709502914790022062049882015
    Line 296, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/21.flash_ctrl_rw_evict_all_en/latest/run.log
```
  UVM_FATAL @ 22637.5 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00000ef8
  UVM_INFO @ 22637.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```