FLASH_CTRL Simulation Results

Sunday June 23 2024 23:02:35 UTC

GitHub Revision: `25e609d6bb`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 43520053114197278442322840927374150239284669988213580416404649115121474470865

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	5.349m	7.381ms	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.610s	57.506us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	46.130s	43.336us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	18.130s	25.799us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.415m	2.363ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.115m	1.297ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	20.690s	176.395us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	18.130s	25.799us	20	20	100.00
		flash_ctrl_csr_aliasing	1.115m	1.297ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.930s	16.786us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.790s	20.255us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.920s	94.344us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	1.856m	58.753us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	37.471m	337.618ms	3	3	100.00
		flash_ctrl_hw_rma_reset	19.985m	270.267ms	20	20	100.00
		flash_ctrl_lcmgr_intg	13.910s	47.264us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	55.029m	1.565s	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	11.242m	4.758ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	3.082m	4.139ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	55.654m	1.590s	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	3.711m	16.974ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	32.070s	78.978us	38	40	95.00
		flash_ctrl_rw_evict_all_en	31.940s	58.702us	40	40	100.00
		flash_ctrl_re_evict	35.760s	73.628us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	9.179m	1.590ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	9.179m	1.590ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	17.414m	37.954ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	29.470s	1.967ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	23.133m	4.559ms	19	20	95.00
V2	error_mp	flash_ctrl_error_mp	40.854m	11.353ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	20.445m	507.757us	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	39.201m	1.162ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	13.910s	47.599us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	4.288m	1.786ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.890s	13.065us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.160s	40.788us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	25.149m	1.322ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	5.013m	38.542ms	50	50	100.00
		flash_ctrl_otp_reset	2.224m	224.223us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	37.471m	337.618ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	4.353m	6.373ms	38	40	95.00
		flash_ctrl_intr_wr	1.815m	19.269ms	9	10	90.00
		flash_ctrl_intr_rd_slow_flash	7.259m	24.646ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	5.230m	147.594ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.736m	7.477ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.218m	11.761ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	28.320s	107.751us	5	5	100.00
		flash_ctrl_ro_derr	2.912m	1.104ms	10	10	100.00
		flash_ctrl_rw_derr	12.637m	3.750ms	4	10	40.00
		flash_ctrl_derr_detect	1.738m	120.189us	5	5	100.00
		flash_ctrl_integrity	12.340m	4.319ms	3	5	60.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	28.260s	167.490us	5	5	100.00
		flash_ctrl_ro_serr	2.541m	2.360ms	10	10	100.00
		flash_ctrl_rw_serr	12.454m	6.087ms	8	10	80.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.558m	9.161ms	4	5	80.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.890m	5.145ms	5	5	100.00
V2	scramble	flash_ctrl_wo	3.827m	21.251ms	20	20	100.00
		flash_ctrl_write_word_sweep	15.270s	39.878us	1	1	100.00
		flash_ctrl_read_word_sweep	17.920s	80.750us	1	1	100.00
		flash_ctrl_ro	2.443m	3.123ms	19	20	95.00
		flash_ctrl_rw	10.973m	13.791ms	18	20	90.00
V2	filesystem_support	flash_ctrl_fs_sup	44.560s	3.482ms	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	20.767m	303.046ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.285m	10.012ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	16.590s	569.614us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.510s	15.973us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	21.000s	51.699us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	21.000s	51.699us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	46.130s	43.336us	5	5	100.00
		flash_ctrl_csr_rw	18.130s	25.799us	20	20	100.00
		flash_ctrl_csr_aliasing	1.115m	1.297ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.200s	170.993us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	46.130s	43.336us	5	5	100.00
		flash_ctrl_csr_rw	18.130s	25.799us	20	20	100.00
		flash_ctrl_csr_aliasing	1.115m	1.297ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.200s	170.993us	20	20	100.00
V2		TOTAL			993	1013	98.03
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.260s	31.368us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.260s	31.368us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.260s	31.368us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.260s	31.368us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.410s	42.008us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.337h	1.275ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.339m	1.283ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.339m	1.283ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.339m	1.283ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	32.150s	213.649us	3	3	100.00
		flash_ctrl_wr_intg	15.610s	288.568us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	5.349m	7.381ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.224m	224.223us	80	80	100.00
		flash_ctrl_disable	22.890s	13.065us	50	50	100.00
		flash_ctrl_sec_info_access	1.444m	5.973ms	50	50	100.00
		flash_ctrl_connect	16.160s	40.788us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.260s	38.709us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	18.130s	25.799us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.260s	31.368us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	18.130s	25.799us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.260s	31.368us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	18.130s	25.799us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.260s	31.368us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.890s	13.065us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	32.150s	213.649us	3	3	100.00
		flash_ctrl_access_after_disable	13.690s	45.302us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.890s	13.065us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	29.470s	1.967ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	10.973m	13.791ms	18	20	90.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	12.454m	6.087ms	8	10	80.00
		flash_ctrl_rw_derr	12.637m	3.750ms	4	10	40.00
		flash_ctrl_integrity	12.340m	4.319ms	3	5	60.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	37.471m	337.618ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.337h	1.275ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.337h	1.275ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.337h	1.275ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.337h	1.275ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	20.950s	906.762us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.290s	15.186us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.220s	24.827us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.337h	1.275ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.337h	1.275ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.337h	1.275ms	5	5	100.00
V2S		TOTAL			144	144	100.00
V3	asymmetric_read_path	flash_ctrl_rd_ooo	44.850s	156.647us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1258	1278	98.44

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	45	81.82
V2S	12	12	12	100.00
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.29	95.71	93.94	98.31	92.52	98.19	97.09	98.24

Failure Buckets

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:289) m_otf_scb [process_read] unexpected double bit error * has 4 failures:
- Test flash_ctrl_integrity has 2 failures.
  - 0.flash_ctrl_integrity.99740238998117816504489739155221282476388812879069905666587093279833463479887
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_integrity/latest/run.log
```
  UVM_ERROR @ 2973313.8 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00002a70
  UVM_INFO @ 2973313.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.flash_ctrl_integrity.61394584289217370261093691512848597618774907737155651770750617947075004324446
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_integrity/latest/run.log
```
  UVM_ERROR @ 2584171.8 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00000200
  UVM_INFO @ 2584171.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_rw_derr has 2 failures.
  - 2.flash_ctrl_rw_derr.35340772702433558120990101358769017115261068520763216058870295529312102545611
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 4262475.7 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00002a00
  UVM_INFO @ 4262475.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.flash_ctrl_rw_derr.57614121159830791111139916009233534952072635164729245291195508646205854649973
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 38414734.6 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00003c00
  UVM_INFO @ 38414734.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 4 failures:

Test flash_ctrl_serr_counter has 1 failures.

2.flash_ctrl_serr_counter.70312555511391420759566431638885947511689450888021334546905460279676270115808
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_serr_counter/latest/run.log

  UVM_ERROR @ 551576.4 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 551576.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_rw_serr has 1 failures.

8.flash_ctrl_rw_serr.106788037330259560108817757986081469770950642207810680712662322816742809453908
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 2713586.1 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 2713586.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_rw has 1 failures.

10.flash_ctrl_rw.60602787418318032770840942839132695911638568102678247178666623410942813273834
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_rw/latest/run.log

  UVM_ERROR @ 270725.0 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 270725.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_ro has 1 failures.

12.flash_ctrl_ro.19489090825105748230577109961216209740256320996786198074742053772368193732631
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_ro/latest/run.log

  UVM_ERROR @ 76910.7 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 76910.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 3 failures:
- Test flash_ctrl_rw_serr has 1 failures.
  - 0.flash_ctrl_rw_serr.62483525948991435659636063831525395382275203372457333523266324849861377341969
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_serr/latest/run.log
```
  Job ID: smart:19194378-5d4b-4a97-b6fb-5bd2614a9f43
```
- Test flash_ctrl_intr_wr has 1 failures.
  - 0.flash_ctrl_intr_wr.23425637001960065970677068483048606468462526704493115712159292399154719114368
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_intr_wr/latest/run.log
```
  Job ID: smart:3d2f6fe0-90c7-4a65-a3bf-f28eeba2d347
```
- Test flash_ctrl_rw has 1 failures.
  - 7.flash_ctrl_rw.8273924118517321559381759787628173855626840223142904701044584186419060209120
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_rw/latest/run.log
```
  Job ID: smart:aa4f8a36-e231-4f5e-aa61-2c7c07301de1
```

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 3 failures:

Test flash_ctrl_rw_derr has 3 failures.

3.flash_ctrl_rw_derr.80123277206250941492579213632663846554617315084290915231546324934229571681063
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_rw_derr/latest/run.log

  UVM_ERROR @ 11419213.7 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (38144286383833010542928 [0x813ce50010160021950] vs 38144286383833010538832 [0x813ce50010160020950])
  UVM_INFO @ 11419213.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.flash_ctrl_rw_derr.28543304605707835104244567696045352986439952081779274518111764820589312000203
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_rw_derr/latest/run.log

  UVM_ERROR @ 1876928.3 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (16546747954657742559330 [0x3810041cc5550201862] vs 16546747954657742690402 [0x3810041cc5550221862])
  UVM_INFO @ 1876928.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 1 failures:
- Test flash_ctrl_rw_evict has 1 failures.
  - 1.flash_ctrl_rw_evict.76660657304644903338232776027451257618674821443711527754962613121576757535261
    Line 287, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_evict/latest/run.log
```
  UVM_ERROR @ 31886.2 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 31886.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 1 failures:
- Test flash_ctrl_rw_derr has 1 failures.
  - 4.flash_ctrl_rw_derr.66547211705031262943020910622024440571733636434763970919711708559888271264192
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 2060353.5 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (3689530003550847911552 [0xc80283b64302004680] vs 3689530003275970004608 [0xc80283b60302004680])
  UVM_INFO @ 2060353.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp e4b06af6_93794c65:ffffffff_93794c* mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 12.flash_ctrl_intr_rd.87578038080043402492860780359323632110446996322399855614835027648014134313274
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 3687527.8 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    4: obs:exp    e4b06af6_93794c65:ffffffff_93794c65  mismatch!!
  UVM_INFO @ 3687527.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *a31813_36e05302:ffffffff_ffffffff mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 13.flash_ctrl_intr_rd.110545172877737342928623809345848223578167777480918124249824095133481993471924
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 1290667.4 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    2: obs:exp    43a31813_36e05302:ffffffff_ffffffff  mismatch!!
  UVM_INFO @ 1290667.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:736) [scoreboard] Check failed exp_data_part[addr] == data (* [*] vs * [*]) read addr:* data: * has 1 failures:
- Test flash_ctrl_rand_ops has 1 failures.
  - 19.flash_ctrl_rand_ops.82511391461879199721581040098151756432024444745911380397831778867174049006417
    Line 1356, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/19.flash_ctrl_rand_ops/latest/run.log
```
  UVM_ERROR @ 61953.3 ns: (flash_ctrl_scoreboard.sv:736) [uvm_test_top.env.scoreboard] Check failed exp_data_part[addr] == data (4147035702 [0xf72ebe36] vs 771278840 [0x2df8c7f8]) read addr:0x80710 data: 0x2df8c7f8
  UVM_INFO @ 61953.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: * has 1 failures:
- Test flash_ctrl_rw_evict has 1 failures.
  - 38.flash_ctrl_rw_evict.48628839642683120107193493119341057535275967818764914342013689714282413956705
    Line 299, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/38.flash_ctrl_rw_evict/latest/run.log
```
  UVM_ERROR @ 36778.5 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: 0x0
  UVM_INFO @ 36778.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```