FLASH_CTRL Simulation Results

Monday June 24 2024 23:02:35 UTC

GitHub Revision: `6e698b4dfe`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 102849012855470111388983783327793201144267754054590670930996118558901483180117

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.629m	88.655us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.140s	90.193us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	46.930s	49.429us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	18.290s	641.097us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.480m	18.210ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	53.940s	667.572us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	20.550s	1.120ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	18.290s	641.097us	20	20	100.00
		flash_ctrl_csr_aliasing	53.940s	667.572us	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.740s	17.424us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	14.090s	116.357us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	27.200s	45.235us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	1.711m	437.080us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	33.663m	167.435ms	3	3	100.00
		flash_ctrl_hw_rma_reset	16.961m	260.238ms	20	20	100.00
		flash_ctrl_lcmgr_intg	14.260s	53.425us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	46.019m	248.656ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	9.517m	19.706ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	3.840m	20.041ms	28	30	93.33
V2	full_memory_access	flash_ctrl_full_mem_access	1.108h	306.181ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.450m	720.575us	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	33.300s	136.062us	39	40	97.50
		flash_ctrl_rw_evict_all_en	32.210s	72.279us	39	40	97.50
		flash_ctrl_re_evict	35.830s	72.684us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	10.896m	2.751ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	10.896m	2.751ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	20.457m	22.898ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	28.900s	2.969ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	25.053m	5.833ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	41.977m	5.885ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	18.380m	1.788ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	44.340m	1.038ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	13.960s	15.624us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	4.619m	3.277ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.580s	51.842us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.280s	35.795us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	28.178m	1.423ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.388m	3.955ms	50	50	100.00
		flash_ctrl_otp_reset	2.228m	74.615us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	33.663m	167.435ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	5.038m	7.065ms	38	40	95.00
		flash_ctrl_intr_wr	1.325m	8.887ms	9	10	90.00
		flash_ctrl_intr_rd_slow_flash	8.627m	203.710ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	6.832m	432.057ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.627m	976.872us	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.243m	1.317ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	29.100s	148.778us	4	5	80.00
		flash_ctrl_ro_derr	2.990m	1.314ms	10	10	100.00
		flash_ctrl_rw_derr	13.948m	9.307ms	5	10	50.00
		flash_ctrl_derr_detect	1.769m	322.700us	5	5	100.00
		flash_ctrl_integrity	12.337m	7.055ms	2	5	40.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	28.660s	85.342us	5	5	100.00
		flash_ctrl_ro_serr	3.023m	2.585ms	10	10	100.00
		flash_ctrl_rw_serr	12.161m	20.295ms	9	10	90.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.380m	836.079us	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.312m	735.037us	4	5	80.00
V2	scramble	flash_ctrl_wo	4.367m	13.745ms	18	20	90.00
		flash_ctrl_write_word_sweep	15.090s	148.208us	1	1	100.00
		flash_ctrl_read_word_sweep	18.810s	1.286ms	1	1	100.00
		flash_ctrl_ro	2.434m	1.071ms	19	20	95.00
		flash_ctrl_rw	11.725m	3.501ms	18	20	90.00
V2	filesystem_support	flash_ctrl_fs_sup	45.830s	317.817us	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	16.514m	167.197ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	2.322m	10.012ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.540s	228.169us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.000s	18.302us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	21.660s	117.729us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	21.660s	117.729us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	46.930s	49.429us	5	5	100.00
		flash_ctrl_csr_rw	18.290s	641.097us	20	20	100.00
		flash_ctrl_csr_aliasing	53.940s	667.572us	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.190s	397.222us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	46.930s	49.429us	5	5	100.00
		flash_ctrl_csr_rw	18.290s	641.097us	20	20	100.00
		flash_ctrl_csr_aliasing	53.940s	667.572us	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.190s	397.222us	20	20	100.00
V2		TOTAL			990	1013	97.73
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.450s	12.873us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.450s	12.873us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.450s	12.873us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.450s	12.873us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.130s	12.461us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.375h	3.177ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.323m	721.708us	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.323m	721.708us	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.323m	721.708us	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	32.250s	62.975us	3	3	100.00
		flash_ctrl_wr_intg	15.470s	88.236us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.629m	88.655us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.228m	74.615us	80	80	100.00
		flash_ctrl_disable	22.580s	51.842us	50	50	100.00
		flash_ctrl_sec_info_access	1.807m	33.420ms	50	50	100.00
		flash_ctrl_connect	16.280s	35.795us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.390s	42.943us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	18.290s	641.097us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.450s	12.873us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	18.290s	641.097us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.450s	12.873us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	18.290s	641.097us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.450s	12.873us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.580s	51.842us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	32.250s	62.975us	3	3	100.00
		flash_ctrl_access_after_disable	13.640s	33.589us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.580s	51.842us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	28.900s	2.969ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	11.725m	3.501ms	18	20	90.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	12.161m	20.295ms	9	10	90.00
		flash_ctrl_rw_derr	13.948m	9.307ms	5	10	50.00
		flash_ctrl_integrity	12.337m	7.055ms	2	5	40.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	33.663m	167.435ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.375h	3.177ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.375h	3.177ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.375h	3.177ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.375h	3.177ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	23.940s	855.141us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.450s	24.417us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.250s	16.478us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.375h	3.177ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.375h	3.177ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.375h	3.177ms	5	5	100.00
V2S		TOTAL			144	144	100.00
V3	asymmetric_read_path	flash_ctrl_rd_ooo	47.330s	334.701us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1255	1278	98.20

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	42	76.36
V2S	12	12	12	100.00
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.30	95.73	93.97	98.31	92.52	98.25	97.09	98.24

Failure Buckets

Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 8 failures:
- Test flash_ctrl_intr_wr has 1 failures.
  - 0.flash_ctrl_intr_wr.24019821804442135693349282039510474312707129265090295998922857758623674834620
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_intr_wr/latest/run.log
```
  Job ID: smart:39530192-20de-403e-b748-7414ff625a2f
```
- Test flash_ctrl_rw_derr has 1 failures.
  - 1.flash_ctrl_rw_derr.27844733696779210513983832769715929950363340660101763673207757641867505546066
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_derr/latest/run.log
```
  Job ID: smart:ab39f259-fd32-4955-8d36-8525e51d78ee
```
- Test flash_ctrl_prog_reset has 2 failures.
  - 1.flash_ctrl_prog_reset.43585438748444340403752397976445316663534202640331230334071343861698864770386
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_prog_reset/latest/run.log
```
  Job ID: smart:ee8e3b1f-5172-46c0-be7a-3e8eeeb568dd
```
  - 28.flash_ctrl_prog_reset.4449806940938968458931796103560467024345617921761938095722883830694884614745
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/28.flash_ctrl_prog_reset/latest/run.log
```
  Job ID: smart:60e99367-a1a4-4310-aa8c-9fe1a5b623cd
```
- Test flash_ctrl_rw has 1 failures.
  - 2.flash_ctrl_rw.74082883965692772711394271568408810682071938419376065021077595007797633860872
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rw/latest/run.log
```
  Job ID: smart:3a758419-3aee-4c4a-813e-8f4fe853a9ca
```
- Test flash_ctrl_integrity has 1 failures.
  - 4.flash_ctrl_integrity.4662918227124737120833768784312422012035453267836420414572887019041919845142
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_integrity/latest/run.log
```
  Job ID: smart:6ae150b4-462b-4191-b4dc-448ab7533fc0
```
- ... and 1 more tests.
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:289) m_otf_scb [process_read] unexpected double bit error * has 6 failures:
- Test flash_ctrl_read_word_sweep_derr has 1 failures.
  - 1.flash_ctrl_read_word_sweep_derr.55299729807329858169252003313169180076439739313428434928895906063107483403011
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_read_word_sweep_derr/latest/run.log
```
  UVM_ERROR @ 31926.6 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x000f26a8
  UVM_INFO @ 31926.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_integrity has 2 failures.
  - 2.flash_ctrl_integrity.13008570524149392916510377191387775731846209342800391588395940073530266186270
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_integrity/latest/run.log
```
  UVM_ERROR @ 3019041.0 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00004800
  UVM_INFO @ 3019041.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.flash_ctrl_integrity.108658718929316050257510193837681084641664796924333248404400654104109824085505
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_integrity/latest/run.log
```
  UVM_ERROR @ 3431132.1 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00003800
  UVM_INFO @ 3431132.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_rw_derr has 3 failures.
  - 6.flash_ctrl_rw_derr.100195416239505313686851220744317670583563590328109996334488406399177716045554
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 2473349.2 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00004298
  UVM_INFO @ 2473349.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.flash_ctrl_rw_derr.29993690570403647994061534865510381445029952608208341412208005783303805883391
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 8208737.5 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00002220
  UVM_INFO @ 8208737.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 3 failures:

Test flash_ctrl_rw has 1 failures.

0.flash_ctrl_rw.104413166657402176878191850467302149834841818538818584214300143410683925898196
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw/latest/run.log

  UVM_ERROR @ 9773103.7 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 9773103.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_ro has 1 failures.

8.flash_ctrl_ro.40442403548033286183062678449812997207773343339599483762226283768702968053673
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_ro/latest/run.log

  UVM_ERROR @ 18692.3 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 18692.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_rw_serr has 1 failures.

9.flash_ctrl_rw_serr.2362969718560068273794332435124394860199794264980227760639094523498549635973
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 2301209.3 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 2301209.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 2 failures:
- Test flash_ctrl_rw_evict_all_en has 1 failures.
  - 14.flash_ctrl_rw_evict_all_en.47005005189248317479194846761102615578086021054131944044874748984104472362295
    Line 290, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/14.flash_ctrl_rw_evict_all_en/latest/run.log
```
  UVM_ERROR @ 8478.9 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 8478.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_rw_evict has 1 failures.
  - 34.flash_ctrl_rw_evict.88224070678917594907018588848035606434183201078262830955187780542195664160288
    Line 287, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/34.flash_ctrl_rw_evict/latest/run.log
```
  UVM_ERROR @ 9708.0 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 9708.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 1 failures:
- Test flash_ctrl_serr_address has 1 failures.
  - 4.flash_ctrl_serr_address.13360848391711051606874643420620240316829228841728170218136185861162498734817
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_serr_address/latest/run.log
```
  UVM_ERROR @ 464638.8 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (25423144157887319773225 [0x5623100020205201029] vs 25423144157887319773224 [0x5623100020205201028])
  UVM_INFO @ 464638.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 1 failures:
- Test flash_ctrl_rw_derr has 1 failures.
  - 4.flash_ctrl_rw_derr.96939871216175119517550902175754389588085762848370194109087348681849885173641
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 4235885.8 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (8015255044969304801408 [0x1b282023cc22105c080] vs 8015255044969304801416 [0x1b282023cc22105c088])
  UVM_INFO @ 4235885.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *ae_3a43138a:ffffffff_ffffffff mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 10.flash_ctrl_intr_rd.983682477566782039704504022892283113604790794017524766271131663918231000755
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 889250.8 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    6: obs:exp    259385ae_3a43138a:ffffffff_ffffffff  mismatch!!
  UVM_INFO @ 889250.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *bbd3063_ff0f87d1:ffffffff_ffffffff mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 25.flash_ctrl_intr_rd.57112456198985986077227567909261365609333310160717298693882158034849623940304
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/25.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 653926.8 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    1: obs:exp    5bbd3063_ff0f87d1:ffffffff_ffffffff  mismatch!!
  UVM_INFO @ 653926.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```