FLASH_CTRL Simulation Results

Tuesday June 25 2024 23:02:40 UTC

GitHub Revision: `3fd3528c8c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 44317642457786780768002458033256869318159334982704173107202396839344093642292

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	4.291m	9.712ms	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	27.730s	25.037us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	45.630s	85.452us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	18.420s	73.831us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.359m	2.285ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.139m	1.319ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	20.200s	393.937us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	18.420s	73.831us	20	20	100.00
		flash_ctrl_csr_aliasing	1.139m	1.319ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	14.200s	24.014us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	14.520s	35.618us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	27.130s	53.854us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	1.543m	118.710us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	36.683m	119.774ms	3	3	100.00
		flash_ctrl_hw_rma_reset	25.442m	630.372ms	20	20	100.00
		flash_ctrl_lcmgr_intg	14.520s	25.088us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	49.377m	263.526ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	8.171m	2.811ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	3.745m	2.670ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.312h	187.823ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.515m	1.462ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	33.550s	33.114us	39	40	97.50
		flash_ctrl_rw_evict_all_en	32.790s	80.172us	40	40	100.00
		flash_ctrl_re_evict	37.280s	277.248us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	11.198m	6.122ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	11.198m	6.122ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	10.381m	14.987ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	32.620s	926.619us	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	19.695m	260.256us	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	41.841m	4.414ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	17.232m	7.990ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	45.231m	959.485us	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	14.520s	23.291us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.794m	5.517ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	23.730s	12.626us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	17.080s	16.731us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	31.351m	988.956us	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.335m	23.634ms	50	50	100.00
		flash_ctrl_otp_reset	2.301m	147.744us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	36.683m	119.774ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	4.872m	6.870ms	40	40	100.00
		flash_ctrl_intr_wr	1.536m	3.405ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	9.182m	29.106ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	4.321m	88.531ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.674m	5.375ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.252m	649.470us	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	28.040s	302.595us	5	5	100.00
		flash_ctrl_ro_derr	2.933m	1.422ms	10	10	100.00
		flash_ctrl_rw_derr	13.014m	46.758ms	7	10	70.00
		flash_ctrl_derr_detect	1.803m	878.660us	5	5	100.00
		flash_ctrl_integrity	12.261m	4.281ms	3	5	60.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	27.510s	82.370us	5	5	100.00
		flash_ctrl_ro_serr	2.662m	2.442ms	10	10	100.00
		flash_ctrl_rw_serr	12.195m	8.862ms	4	10	40.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.997m	5.299ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.747m	1.197ms	4	5	80.00
V2	scramble	flash_ctrl_wo	4.562m	10.885ms	19	20	95.00
		flash_ctrl_write_word_sweep	14.620s	28.055us	0	1	0.00
		flash_ctrl_read_word_sweep	19.060s	833.503us	1	1	100.00
		flash_ctrl_ro	2.365m	10.073ms	16	20	80.00
		flash_ctrl_rw	11.313m	28.856ms	17	20	85.00
V2	filesystem_support	flash_ctrl_fs_sup	44.360s	715.734us	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	18.507m	165.677ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.306m	10.013ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.670s	180.885us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	15.280s	80.170us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	20.740s	103.870us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	20.740s	103.870us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	45.630s	85.452us	5	5	100.00
		flash_ctrl_csr_rw	18.420s	73.831us	20	20	100.00
		flash_ctrl_csr_aliasing	1.139m	1.319ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	37.390s	158.004us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	45.630s	85.452us	5	5	100.00
		flash_ctrl_csr_rw	18.420s	73.831us	20	20	100.00
		flash_ctrl_csr_aliasing	1.139m	1.319ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	37.390s	158.004us	20	20	100.00
V2		TOTAL			991	1013	97.83
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.590s	42.248us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.590s	42.248us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.590s	42.248us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.590s	42.248us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.470s	32.208us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.392h	1.504ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.819m	971.359us	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.819m	971.359us	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.819m	971.359us	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	31.970s	64.858us	3	3	100.00
		flash_ctrl_wr_intg	15.900s	73.166us	1	3	33.33
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	4.291m	9.712ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.301m	147.744us	80	80	100.00
		flash_ctrl_disable	23.730s	12.626us	50	50	100.00
		flash_ctrl_sec_info_access	1.603m	17.715ms	50	50	100.00
		flash_ctrl_connect	17.080s	16.731us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.910s	19.639us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	18.420s	73.831us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.590s	42.248us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	18.420s	73.831us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.590s	42.248us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	18.420s	73.831us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.590s	42.248us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	23.730s	12.626us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	31.970s	64.858us	3	3	100.00
		flash_ctrl_access_after_disable	14.400s	15.184us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	23.730s	12.626us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	32.620s	926.619us	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	11.313m	28.856ms	17	20	85.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	12.195m	8.862ms	4	10	40.00
		flash_ctrl_rw_derr	13.014m	46.758ms	7	10	70.00
		flash_ctrl_integrity	12.261m	4.281ms	3	5	60.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	36.683m	119.774ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.392h	1.504ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.392h	1.504ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.392h	1.504ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.392h	1.504ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	22.400s	826.129us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	15.420s	15.681us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	15.250s	74.340us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.392h	1.504ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.392h	1.504ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.392h	1.504ms	5	5	100.00
V2S		TOTAL			142	144	98.61
V3	asymmetric_read_path	flash_ctrl_rd_ooo	48.280s	167.678us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1254	1278	98.12

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	46	83.64
V2S	12	12	11	91.67
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.12	95.67	93.90	98.31	91.16	98.17	97.38	98.21

Failure Buckets

UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 8 failures:

Test flash_ctrl_rw_serr has 2 failures.

0.flash_ctrl_rw_serr.39545123515649633679915342858677816596825309164337862986277866370714063903053
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 1569106.7 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 1569106.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.flash_ctrl_rw_serr.28364562642099287322697617336305681103052176060096746121782731536282875204666
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 4859088.2 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 4859088.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_ro has 4 failures.

1.flash_ctrl_ro.16228006506697286854190107335772812196179211326891137435901560054873044161304
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_ro/latest/run.log

  UVM_ERROR @ 34622.0 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 34622.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.flash_ctrl_ro.82795455586503513854898390243668980506841455276549073074087139989223539121562
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_ro/latest/run.log

  UVM_ERROR @ 1343884.8 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 1343884.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test flash_ctrl_serr_address has 1 failures.

4.flash_ctrl_serr_address.6670953538032571146361550518675976953270977505111772023760972269027185224213
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_serr_address/latest/run.log

  UVM_ERROR @ 243262.9 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 243262.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_rw has 1 failures.

18.flash_ctrl_rw.55597220904377186660298447930207183085361535224220257596187363032891001317713
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/18.flash_ctrl_rw/latest/run.log

  UVM_ERROR @ 567424.3 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 567424.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 6 failures:
- Test flash_ctrl_rw_derr has 2 failures.
  - 1.flash_ctrl_rw_derr.9895669863561530107623821829826473881277824042017432294568483469257780417409
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_derr/latest/run.log
```
  Job ID: smart:56ffb582-59d4-481a-9b1c-1397cb874ee2
```
  - 7.flash_ctrl_rw_derr.105283154234131630275196146066854286055914313075975097640062658805561507164691
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_rw_derr/latest/run.log
```
  Job ID: smart:6cd25541-4d43-4011-a849-86ee3596994b
```
- Test flash_ctrl_wo has 1 failures.
  - 4.flash_ctrl_wo.2298419641936254134239864428902570696595370296058385094892215154739245687262
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_wo/latest/run.log
```
  Job ID: smart:0ae52982-a9bc-4e3b-8163-ca66adda03cc
```
- Test flash_ctrl_integrity has 1 failures.
  - 4.flash_ctrl_integrity.23234516628358698777264111494210196038745542182127201037106740258871995889562
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_integrity/latest/run.log
```
  Job ID: smart:17279205-9995-4bf3-a0db-e21da23bb2a1
```
- Test flash_ctrl_rw has 2 failures.
  - 11.flash_ctrl_rw.59941907970251828025072776440815048075336044397495621574405903311877411832834
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/11.flash_ctrl_rw/latest/run.log
```
  Job ID: smart:278ee857-fe71-4bce-86cc-5dd584508f76
```
  - 19.flash_ctrl_rw.107848483915948056663047327267468893283785988916773032255029367515825841187455
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/19.flash_ctrl_rw/latest/run.log
```
  Job ID: smart:882680e5-4341-41fd-a6e7-8226db3bf28f
```

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 5 failures:

Test flash_ctrl_integrity has 1 failures.

0.flash_ctrl_integrity.90241296647709025156719630171604321499479198261823144280543947003141122302425
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_integrity/latest/run.log

  UVM_ERROR @ 24270583.8 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (812834740952199881997 [0x2c10591a502088650d] vs 9961255594619773275145 [0x21c00310250081a4c09])
  UVM_INFO @ 24270583.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_rw_serr has 4 failures.

1.flash_ctrl_rw_serr.43739373151198174280822468229947819442767079931270208015061756978180644251716
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 6825341.6 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (452698467383613374720 [0x188a7409960c08c100] vs 452698467383613374464 [0x188a7409960c08c000])
  UVM_INFO @ 6825341.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.flash_ctrl_rw_serr.103987957755034501556634201267028093670304285676906440582231029474792811214483
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 6909387.9 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (33075591452729379652480 [0x701080a304369080380] vs 33075591452729379718016 [0x701080a304369090380])
  UVM_INFO @ 6909387.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_write_word_sweep_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 1 failures:
- Test flash_ctrl_write_word_sweep has 1 failures.
  - 0.flash_ctrl_write_word_sweep.62853225647996222635462417188178809916030817035894455005063869712351802088991
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_write_word_sweep/latest/run.log
```
  UVM_FATAL @ 28054.6 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_write_word_sweep_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00000800
  UVM_INFO @ 28054.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [wdata_page0_comp_bank0] *: obs:exp *e6270_f0a83758:7ce7adb2_12a4ee* mismatch!! has 1 failures:
- Test flash_ctrl_wr_intg has 1 failures.
  - 1.flash_ctrl_wr_intg.383151802123870433656056495105270355392201212875371216993336759848587338865
    Line 299, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_wr_intg/latest/run.log
```
  UVM_ERROR @ 47191.3 ns: (flash_ctrl_otf_scoreboard.sv:375) [wdata_page0_comp_bank0]    0: obs:exp    146e6270_f0a83758:7ce7adb2_12a4ee72  mismatch!!
  UVM_INFO @ 47191.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:367) [wdata_page0_comp_bank0] *: obs:exp *_*_2df77e14_fd8c28dd:*_*_*_cf* mismatch!! has 1 failures:
- Test flash_ctrl_wr_intg has 1 failures.
  - 2.flash_ctrl_wr_intg.101920036118681947613056265108483169563403778619792060066400866065296507427135
    Line 299, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_wr_intg/latest/run.log
```
  UVM_ERROR @ 25192.9 ns: (flash_ctrl_otf_scoreboard.sv:367) [wdata_page0_comp_bank0]    0: obs:exp    09_1_2df77e14_fd8c28dd:59_1_12188771_cf719206  mismatch!!
  UVM_INFO @ 25192.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:289) m_otf_scb [process_read] unexpected double bit error * has 1 failures:
- Test flash_ctrl_rw_derr has 1 failures.
  - 5.flash_ctrl_rw_derr.18487515684293043635526339252561183693284240728137869538305769583363593056600
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 23352279.4 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00003000
  UVM_INFO @ 23352279.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 1 failures:
- Test flash_ctrl_rw_evict has 1 failures.
  - 21.flash_ctrl_rw_evict.70145644287176593189664411604144906943053818136083962330834840329885236852559
    Line 299, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/21.flash_ctrl_rw_evict/latest/run.log
```
  UVM_ERROR @ 26169.2 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 26169.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```