FLASH_CTRL Simulation Results

Wednesday June 26 2024 23:02:36 UTC

GitHub Revision: `be1c4a4f52`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 44766564427213563291105655232733134394512207819884794315335669279596867428010

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.254m	150.059us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	27.050s	23.698us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	47.100s	52.724us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	18.420s	171.041us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	2.401m	58.440ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.197m	12.970ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	20.570s	81.797us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	18.420s	171.041us	20	20	100.00
		flash_ctrl_csr_aliasing	1.197m	12.970ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	14.190s	16.168us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	14.090s	16.462us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	28.500s	21.358us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	1.891m	119.720us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	34.384m	120.855ms	3	3	100.00
		flash_ctrl_hw_rma_reset	25.866m	760.490ms	20	20	100.00
		flash_ctrl_lcmgr_intg	15.270s	46.741us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	46.852m	245.532ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	10.604m	18.618ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	4.000m	5.337ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.056h	48.917ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.370m	704.250us	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	33.090s	232.657us	39	40	97.50
		flash_ctrl_rw_evict_all_en	32.690s	61.220us	38	40	95.00
		flash_ctrl_re_evict	37.640s	117.986us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	9.677m	1.403ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	9.677m	1.403ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	10.085m	37.084ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	28.600s	2.119ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	19.277m	255.117us	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	45.103m	30.181ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	15.704m	692.361us	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	46.240m	3.423ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	14.330s	150.158us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	4.297m	4.474ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	23.720s	37.267us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	17.550s	14.314us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	26.639m	1.397ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.209m	4.430ms	50	50	100.00
		flash_ctrl_otp_reset	2.307m	135.191us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	34.384m	120.855ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	4.116m	1.690ms	38	40	95.00
		flash_ctrl_intr_wr	1.327m	2.458ms	7	10	70.00
		flash_ctrl_intr_rd_slow_flash	9.137m	48.302ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	3.824m	100.736ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.670m	2.036ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.288m	5.863ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	29.490s	76.957us	5	5	100.00
		flash_ctrl_ro_derr	3.074m	687.069us	10	10	100.00
		flash_ctrl_rw_derr	13.378m	8.273ms	9	10	90.00
		flash_ctrl_derr_detect	1.830m	127.040us	5	5	100.00
		flash_ctrl_integrity	12.620m	10.486ms	1	5	20.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	29.610s	427.855us	5	5	100.00
		flash_ctrl_ro_serr	3.180m	664.966us	10	10	100.00
		flash_ctrl_rw_serr	14.986m	4.172ms	4	10	40.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.309m	7.092ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.537m	10.027ms	5	5	100.00
V2	scramble	flash_ctrl_wo	4.568m	6.868ms	19	20	95.00
		flash_ctrl_write_word_sweep	14.900s	70.150us	1	1	100.00
		flash_ctrl_read_word_sweep	19.810s	79.704us	1	1	100.00
		flash_ctrl_ro	2.776m	3.910ms	20	20	100.00
		flash_ctrl_rw	12.648m	16.623ms	19	20	95.00
V2	filesystem_support	flash_ctrl_fs_sup	55.020s	3.905ms	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	18.921m	284.498ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.221m	10.012ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.750s	46.116us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.770s	55.150us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	20.590s	238.993us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	20.590s	238.993us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	47.100s	52.724us	5	5	100.00
		flash_ctrl_csr_rw	18.420s	171.041us	20	20	100.00
		flash_ctrl_csr_aliasing	1.197m	12.970ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.880s	173.815us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	47.100s	52.724us	5	5	100.00
		flash_ctrl_csr_rw	18.420s	171.041us	20	20	100.00
		flash_ctrl_csr_aliasing	1.197m	12.970ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.880s	173.815us	20	20	100.00
V2		TOTAL			992	1013	97.93
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.390s	35.728us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.390s	35.728us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.390s	35.728us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.390s	35.728us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.900s	14.418us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.394h	13.536ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.533m	836.776us	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.533m	836.776us	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.533m	836.776us	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	32.440s	240.799us	3	3	100.00
		flash_ctrl_wr_intg	15.840s	44.876us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.254m	150.059us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.307m	135.191us	80	80	100.00
		flash_ctrl_disable	23.720s	37.267us	50	50	100.00
		flash_ctrl_sec_info_access	1.508m	2.318ms	50	50	100.00
		flash_ctrl_connect	17.550s	14.314us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	15.690s	20.518us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	18.420s	171.041us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.390s	35.728us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	18.420s	171.041us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.390s	35.728us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	18.420s	171.041us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.390s	35.728us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	23.720s	37.267us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	32.440s	240.799us	3	3	100.00
		flash_ctrl_access_after_disable	14.100s	34.731us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	23.720s	37.267us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	28.600s	2.119ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	12.648m	16.623ms	19	20	95.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	14.986m	4.172ms	4	10	40.00
		flash_ctrl_rw_derr	13.378m	8.273ms	9	10	90.00
		flash_ctrl_integrity	12.620m	10.486ms	1	5	20.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	34.384m	120.855ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.394h	13.536ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.394h	13.536ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.394h	13.536ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.394h	13.536ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	25.950s	816.020us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.710s	23.718us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.840s	15.366us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.394h	13.536ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.394h	13.536ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.394h	13.536ms	5	5	100.00
V2S		TOTAL			144	144	100.00
V3	asymmetric_read_path	flash_ctrl_rd_ooo	45.480s	180.273us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1257	1278	98.36

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	46	83.64
V2S	12	12	12	100.00
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.30	95.73	93.99	98.31	92.52	98.25	97.09	98.21

Failure Buckets

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 9 failures:

Test flash_ctrl_rw_serr has 4 failures.

0.flash_ctrl_rw_serr.58776520605007506536590398218126844176971397824122231089990736153814562554035
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 3631299.9 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (9233742846484300548 [0x8024d83248004304] vs 9224735647229559556 [0x8004d83248004304])
  UVM_INFO @ 3631299.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.flash_ctrl_rw_serr.11142787529568578527775881856560487570405291151188094929300840166616501932140
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 3294129.4 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (38112139761241173401816 [0x81210304214050220d8] vs 38112139761172453925080 [0x81210304204050220d8])
  UVM_INFO @ 3294129.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test flash_ctrl_rw_derr has 1 failures.

1.flash_ctrl_rw_derr.96192628745492133694312968275008291756374909852269185980940132417498882864099
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_derr/latest/run.log

  UVM_ERROR @ 9136122.3 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (5720333965506692818696 [0x1361994ba000408a708] vs 5729557337543547594504 [0x1369994ba000408a708])
  UVM_INFO @ 9136122.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_integrity has 4 failures.

1.flash_ctrl_integrity.70526570509494838484080137550445836678327248979362896401692902954624080979918
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_integrity/latest/run.log

  UVM_ERROR @ 6261282.8 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (4740814388184802935449 [0x1010004202498044299] vs 23630292670394635651097 [0x501003001114d000819])
  UVM_INFO @ 6261282.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.flash_ctrl_integrity.70618730966738962343597026611868583843514394736626172104048828762118809161529
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_integrity/latest/run.log

  UVM_ERROR @ 1057732.0 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (14433428850634305602564 [0x30e70101c1184608404] vs 5498290594562554594560 [0x12a101c349004620500])
  UVM_INFO @ 1057732.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 5 failures:
- Test flash_ctrl_intr_wr has 3 failures.
  - 0.flash_ctrl_intr_wr.73835190063363217318137586578563520137082442414112582515829863042419319635423
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_intr_wr/latest/run.log
```
  Job ID: smart:c2990c39-2f74-4e0f-8e59-dec3878081bb
```
  - 4.flash_ctrl_intr_wr.3705890208819402470934599164951098286625286421359810236695312592956135606946
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_intr_wr/latest/run.log
```
  Job ID: smart:354455d8-1952-43c2-a95a-1457fa4e746b
```
  - ... and 1 more failures.
- Test flash_ctrl_wo has 1 failures.
  - 1.flash_ctrl_wo.42803073835353082979972327457122462259420724797292534405333563757483752138841
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_wo/latest/run.log
```
  Job ID: smart:db7c074f-ce21-4ce3-ba64-dc305fe914e7
```
- Test flash_ctrl_rw has 1 failures.
  - 17.flash_ctrl_rw.94781710047924918745893970592713121221871617876706440157543725437242981551637
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/17.flash_ctrl_rw/latest/run.log
```
  Job ID: smart:6fd99a2c-e472-4cf6-b987-d41c1ebf860d
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 2 failures:
- Test flash_ctrl_rw_evict_all_en has 1 failures.
  - 4.flash_ctrl_rw_evict_all_en.92795714292781302268271203032054304361360877035569488247412937110884261587321
    Line 286, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw_evict_all_en/latest/run.log
```
  UVM_ERROR @ 9346.7 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 9346.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_rw_evict has 1 failures.
  - 32.flash_ctrl_rw_evict.104511795494914827301950886283410350043626713838046894913156464136429277133852
    Line 290, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/32.flash_ctrl_rw_evict/latest/run.log
```
  UVM_ERROR @ 8508.7 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 8508.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp f219646d_778fe1f2:ffffffff_ffffffff mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 0.flash_ctrl_intr_rd.56682227211133608451212444669659952950260887425978655913656077833898489931675
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 448606.1 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    5: obs:exp    f219646d_778fe1f2:ffffffff_ffffffff  mismatch!!
  UVM_INFO @ 448606.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 1 failures:
- Test flash_ctrl_rw_serr has 1 failures.
  - 2.flash_ctrl_rw_serr.87401835556756211429231326363651783136152613769197265891816962981142215348404
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rw_serr/latest/run.log
```
  UVM_ERROR @ 834364.0 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 834364.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 1 failures:
- Test flash_ctrl_rw_serr has 1 failures.
  - 7.flash_ctrl_rw_serr.5468881106568373490221401856814838699880838778350733995786871860553731122088
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_rw_serr/latest/run.log
```
  UVM_ERROR @ 5283844.9 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (3541779982853949500074 [0xc00012314046c22aaa] vs 3541779982853949500066 [0xc00012314046c22aa2])
  UVM_INFO @ 5283844.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *c6ab276_d2c847aa:ffffffff_ffffffff mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 35.flash_ctrl_intr_rd.41309346601276176234758770972177960440761408635187677248075750197873137356655
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/35.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 1375468.8 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    2: obs:exp    5c6ab276_d2c847aa:ffffffff_ffffffff  mismatch!!
  UVM_INFO @ 1375468.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 1 failures:
- Test flash_ctrl_rw_evict_all_en has 1 failures.
  - 36.flash_ctrl_rw_evict_all_en.21746466186113443554186082183423357988255129441780480962961344192619161546901
    Line 292, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/36.flash_ctrl_rw_evict_all_en/latest/run.log
```
  UVM_FATAL @ 50774.1 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x000014e0
  UVM_INFO @ 50774.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```