FLASH_CTRL Simulation Results

Thursday June 27 2024 23:02:31 UTC

GitHub Revision: `8db2a18db1`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 100513533386727882033709335126269317053614297947080434367729937568368619502352

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	4.587m	14.990ms	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.820s	13.970us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	46.200s	85.459us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	18.590s	277.953us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.541m	6.424ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.042m	1.244ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	20.000s	75.360us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	18.590s	277.953us	20	20	100.00
		flash_ctrl_csr_aliasing	1.042m	1.244ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	14.110s	28.557us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.700s	39.957us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	27.160s	25.827us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	2.169m	143.382us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	30.721m	98.713ms	3	3	100.00
		flash_ctrl_hw_rma_reset	17.646m	240.214ms	20	20	100.00
		flash_ctrl_lcmgr_intg	14.400s	26.923us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	41.919m	243.874ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	9.204m	44.495ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	3.503m	5.290ms	29	30	96.67
V2	full_memory_access	flash_ctrl_full_mem_access	1.189h	48.915ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	3.027m	1.414ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	32.180s	30.995us	37	40	92.50
		flash_ctrl_rw_evict_all_en	32.200s	32.087us	38	40	95.00
		flash_ctrl_re_evict	35.790s	343.255us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	10.032m	4.246ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	10.032m	4.246ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	15.324m	19.392ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	29.490s	766.126us	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	25.123m	1.538ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	40.837m	14.697ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	18.596m	3.876ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	51.201m	2.916ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	14.190s	48.263us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.365m	17.330ms	3	5	60.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.550s	16.900us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	17.050s	13.680us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	31.037m	1.917ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.802m	12.560ms	50	50	100.00
		flash_ctrl_otp_reset	2.273m	144.444us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	30.721m	98.713ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	4.705m	6.524ms	38	40	95.00
		flash_ctrl_intr_wr	1.374m	19.799ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	7.031m	53.927ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	3.976m	56.311ms	9	10	90.00
V2	invalid_op	flash_ctrl_invalid_op	1.638m	4.033ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.274m	951.428us	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	27.090s	280.535us	5	5	100.00
		flash_ctrl_ro_derr	3.037m	702.445us	10	10	100.00
		flash_ctrl_rw_derr	14.160m	7.930ms	6	10	60.00
		flash_ctrl_derr_detect	1.777m	192.313us	5	5	100.00
		flash_ctrl_integrity	11.057m	4.044ms	1	5	20.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	27.420s	97.094us	4	5	80.00
		flash_ctrl_ro_serr	2.344m	1.015ms	10	10	100.00
		flash_ctrl_rw_serr	12.151m	4.426ms	3	10	30.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.770m	2.294ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	2.044m	21.576ms	5	5	100.00
V2	scramble	flash_ctrl_wo	4.606m	13.249ms	18	20	90.00
		flash_ctrl_write_word_sweep	15.160s	41.846us	1	1	100.00
		flash_ctrl_read_word_sweep	18.590s	85.700us	1	1	100.00
		flash_ctrl_ro	2.450m	9.704ms	20	20	100.00
		flash_ctrl_rw	11.400m	17.541ms	18	20	90.00
V2	filesystem_support	flash_ctrl_fs_sup	43.740s	1.733ms	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	17.416m	159.333ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	3.056m	10.019ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	15.110s	277.651us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.580s	17.660us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	21.180s	66.576us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	21.180s	66.576us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	46.200s	85.459us	5	5	100.00
		flash_ctrl_csr_rw	18.590s	277.953us	20	20	100.00
		flash_ctrl_csr_aliasing	1.042m	1.244ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.000s	2.102ms	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	46.200s	85.459us	5	5	100.00
		flash_ctrl_csr_rw	18.590s	277.953us	20	20	100.00
		flash_ctrl_csr_aliasing	1.042m	1.244ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.000s	2.102ms	20	20	100.00
V2		TOTAL			982	1013	96.94
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.190s	42.306us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.190s	42.306us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.190s	42.306us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.190s	42.306us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.640s	11.634us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.342h	1.013ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.028m	3.089ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.028m	3.089ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.028m	3.089ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	31.800s	65.346us	3	3	100.00
		flash_ctrl_wr_intg	15.490s	87.201us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	4.587m	14.990ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.273m	144.444us	80	80	100.00
		flash_ctrl_disable	22.550s	16.900us	50	50	100.00
		flash_ctrl_sec_info_access	1.609m	18.310ms	50	50	100.00
		flash_ctrl_connect	17.050s	13.680us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.260s	70.014us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	18.590s	277.953us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.190s	42.306us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	18.590s	277.953us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.190s	42.306us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	18.590s	277.953us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.190s	42.306us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.550s	16.900us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	31.800s	65.346us	3	3	100.00
		flash_ctrl_access_after_disable	13.960s	15.706us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.550s	16.900us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	29.490s	766.126us	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	11.400m	17.541ms	18	20	90.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	12.151m	4.426ms	3	10	30.00
		flash_ctrl_rw_derr	14.160m	7.930ms	6	10	60.00
		flash_ctrl_integrity	11.057m	4.044ms	1	5	20.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	30.721m	98.713ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.342h	1.013ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.342h	1.013ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.342h	1.013ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.342h	1.013ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	19.390s	776.250us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.510s	30.980us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	18.980s	304.686us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.342h	1.013ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.342h	1.013ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.342h	1.013ms	5	5	100.00
V2S		TOTAL			144	144	100.00
V3	asymmetric_read_path	flash_ctrl_rd_ooo	48.240s	545.029us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1247	1278	97.57

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	43	78.18
V2S	12	12	12	100.00
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.33	95.70	93.97	98.31	92.52	98.19	97.38	98.21

Failure Buckets

Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 11 failures:
- Test flash_ctrl_rw_serr has 2 failures.
  - 0.flash_ctrl_rw_serr.80305053014054357639108801084663562441365352397313166827547625787113301268802
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_serr/latest/run.log
```
  Job ID: smart:6b114341-12bf-4197-83d0-faaf44c778db
```
  - 5.flash_ctrl_rw_serr.115417637996915655140358272226338234977524226418052010776372603810872506495385
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_rw_serr/latest/run.log
```
  Job ID: smart:ac662d3e-fb8e-45ec-844a-984deb712dbd
```
- Test flash_ctrl_integrity has 2 failures.
  - 1.flash_ctrl_integrity.71376923749250655961820665042110756756413386564560225089807777437612025310362
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_integrity/latest/run.log
```
  Job ID: smart:38611827-9bc2-492b-a563-a2ff9672ac80
```
  - 3.flash_ctrl_integrity.49801474431018599692113906549213927305135295337979034356737603495673183143887
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_integrity/latest/run.log
```
  Job ID: smart:8b02808e-21b5-41cb-b4cd-53f22486ab53
```
- Test flash_ctrl_intr_wr_slow_flash has 1 failures.
  - 4.flash_ctrl_intr_wr_slow_flash.44449148344769638588091366702119397321934658417137552135263774430543149427450
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_intr_wr_slow_flash/latest/run.log
```
  Job ID: smart:015a9d03-c2b7-4d85-b80c-aa043cf21747
```
- Test flash_ctrl_rw_derr has 1 failures.
  - 8.flash_ctrl_rw_derr.5252767799251217143668237290573246362005372835738330273060587185619539105072
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_rw_derr/latest/run.log
```
  Job ID: smart:ee4a0e87-96eb-4f80-b90c-e6ea421ce41d
```
- Test flash_ctrl_rw has 2 failures.
  - 10.flash_ctrl_rw.22012839572781847936407997561005510927961290293670356915665285998893461874667
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_rw/latest/run.log
```
  Job ID: smart:1195c340-2fac-4f03-8b07-e9bb8c78bf82
```
  - 19.flash_ctrl_rw.92756020154663883654560009497804979562215092045358135484195867105922188352447
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/19.flash_ctrl_rw/latest/run.log
```
  Job ID: smart:a947561e-d53f-4ef2-939c-740795073732
```
- ... and 2 more tests.

UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 5 failures:

Test flash_ctrl_read_word_sweep_serr has 1 failures.

1.flash_ctrl_read_word_sweep_serr.11310560126605082007797401845367720059751505338391126866965943850794205119396
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_read_word_sweep_serr/latest/run.log

  UVM_ERROR @ 57234.9 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 57234.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_rw_serr has 4 failures.

1.flash_ctrl_rw_serr.18873673691177285467305586316011993141793917389639432092588190542601578391841
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 1277524.1 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 1277524.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.flash_ctrl_rw_serr.62045296457229144121341998607794649850466956627185379683783001273329702803575
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 5663178.5 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 5663178.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 4 failures:

Test flash_ctrl_rw_evict_all_en has 2 failures.

10.flash_ctrl_rw_evict_all_en.110735866453490946263431813761985974196829908129461761772021110593502309230629
Line 290, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_ERROR @ 33767.7 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 33767.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

18.flash_ctrl_rw_evict_all_en.6702086974771879562389086163497440944240903131157529920412599209495068435792
Line 296, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/18.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_ERROR @ 18659.6 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 18659.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_rw_evict has 2 failures.

18.flash_ctrl_rw_evict.18826267304290635569298457559526202332069793139020543146921853666234396028742
Line 292, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/18.flash_ctrl_rw_evict/latest/run.log

  UVM_ERROR @ 32950.8 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 32950.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

28.flash_ctrl_rw_evict.84030353905820657936631455192966675823511941897703114834353811557171879733461
Line 288, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/28.flash_ctrl_rw_evict/latest/run.log

  UVM_ERROR @ 8545.1 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 8545.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 3 failures:

Test flash_ctrl_integrity has 1 failures.

0.flash_ctrl_integrity.71964917394717120194917494312909925558832361420344731194053504160117444657356
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_integrity/latest/run.log

  UVM_ERROR @ 12657490.8 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (592385782406042363392 [0x201d01128100002600] vs 38959850083313266131464 [0x840048850a418130208])
  UVM_INFO @ 12657490.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_rw_derr has 1 failures.

2.flash_ctrl_rw_derr.54704121581875254727224446928899973041651427877444234268650053147814622437773
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rw_derr/latest/run.log

  UVM_ERROR @ 6468843.8 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (5912253573762844210281 [0x140810024e018103469] vs 5912253573762844243049 [0x140810024e01810b469])
  UVM_INFO @ 6468843.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_rw_serr has 1 failures.

6.flash_ctrl_rw_serr.91021449229342641156038508029776717885865323352006224911672284778186166030744
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 4582289.3 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (39588011098777936502808 [0x86212048c110068a018] vs 1809079235820774793240 [0x6212048c110068a018])
  UVM_INFO @ 4582289.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:289) m_otf_scb [process_read] unexpected double bit error * has 3 failures:
- Test flash_ctrl_integrity has 1 failures.
  - 2.flash_ctrl_integrity.96186995397467134481973073975291389291223890862706675377046360418279454887076
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_integrity/latest/run.log
```
  UVM_ERROR @ 5101203.4 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00004000
  UVM_INFO @ 5101203.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_rw_derr has 2 failures.
  - 4.flash_ctrl_rw_derr.43844770018081846778495882252602249934820950123628588648945517689729191529911
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 10788034.1 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00004060
  UVM_INFO @ 10788034.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.flash_ctrl_rw_derr.71929078857866727532539714715168333857931474778893477469904759154877706870461
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 2747289.2 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x000c00b0
  UVM_INFO @ 2747289.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_otf_item.sv:247) [rd_scr] ecc error is detected has 2 failures:
- Test flash_ctrl_oversize_error has 2 failures.
  - 0.flash_ctrl_oversize_error.1622604365338440496885451845665295858778877124806710523439107816929292176479
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_oversize_error/latest/run.log
```
  UVM_ERROR @ 1750652.0 ns: (flash_otf_item.sv:247) [rd_scr] ecc error is detected
  UVM_INFO @ 1750652.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.flash_ctrl_oversize_error.61665446244173318448933662774225553158178976329289628993086266777229062742326
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_oversize_error/latest/run.log
```
  UVM_ERROR @ 625194.4 ns: (flash_otf_item.sv:247) [rd_scr] ecc error is detected
  UVM_INFO @ 625194.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp a9d711a0_daee1d17:ffffffff_ffffffff mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 16.flash_ctrl_intr_rd.5027049939252139911225590115634721098057371704589601264755798055279262300763
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/16.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 5995569.1 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    7: obs:exp    a9d711a0_daee1d17:ffffffff_ffffffff  mismatch!!
  UVM_INFO @ 5995569.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 1 failures:
- Test flash_ctrl_rw_evict has 1 failures.
  - 25.flash_ctrl_rw_evict.63744736906850534666909949998132357336945388203616820393085623323602230466283
    Line 297, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/25.flash_ctrl_rw_evict/latest/run.log
```
  UVM_FATAL @ 13172.2 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00083e60
  UVM_INFO @ 13172.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *f5f585c_ceae13f5:ffffffff_ceae13f* mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 29.flash_ctrl_intr_rd.19566481550911465761588120301143649045084693303736187881789906319697791911557
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/29.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 142018.4 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    2: obs:exp    2f5f585c_ceae13f5:ffffffff_ceae13f5  mismatch!!
  UVM_INFO @ 142018.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```