FLASH_CTRL Simulation Results

Friday June 28 2024 23:02:02 UTC

GitHub Revision: `3d5220a43f`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 73442097946972310753089853920865571566707682704390544987111276126114608747389

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.607m	106.838us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.700s	16.569us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	39.870s	79.128us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	18.510s	67.152us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.384m	6.526ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.095m	3.397ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	20.680s	157.556us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	18.510s	67.152us	20	20	100.00
		flash_ctrl_csr_aliasing	1.095m	3.397ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.750s	93.241us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.880s	30.690us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	27.750s	72.612us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	2.102m	70.239us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	35.249m	448.458ms	3	3	100.00
		flash_ctrl_hw_rma_reset	16.203m	60.138ms	20	20	100.00
		flash_ctrl_lcmgr_intg	14.350s	25.636us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	37.212m	586.981ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	8.545m	13.946ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	3.410m	11.690ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.154h	101.735ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.568m	6.392ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	32.970s	70.052us	40	40	100.00
		flash_ctrl_rw_evict_all_en	32.610s	40.580us	38	40	95.00
		flash_ctrl_re_evict	37.650s	974.893us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	8.685m	1.396ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	8.685m	1.396ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	17.132m	20.148ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	30.770s	508.190us	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	21.834m	626.867us	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	42.040m	5.195ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	16.063m	5.485ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	46.303m	2.226ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	14.110s	15.494us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.857m	2.895ms	4	5	80.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.860s	44.741us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	17.400s	37.081us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	32.091m	1.369ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.530m	13.837ms	50	50	100.00
		flash_ctrl_otp_reset	2.299m	42.721us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	35.249m	448.458ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	4.538m	6.419ms	39	40	97.50
		flash_ctrl_intr_wr	1.553m	10.848ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	7.783m	248.054ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	4.339m	111.678ms	9	10	90.00
V2	invalid_op	flash_ctrl_invalid_op	1.685m	19.339ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.256m	3.961ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	28.160s	153.410us	5	5	100.00
		flash_ctrl_ro_derr	2.966m	3.325ms	10	10	100.00
		flash_ctrl_rw_derr	13.805m	18.894ms	8	10	80.00
		flash_ctrl_derr_detect	1.786m	121.212us	5	5	100.00
		flash_ctrl_integrity	11.984m	3.293ms	1	5	20.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	28.060s	80.930us	5	5	100.00
		flash_ctrl_ro_serr	2.735m	1.502ms	10	10	100.00
		flash_ctrl_rw_serr	12.114m	8.921ms	6	10	60.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.973m	4.575ms	4	5	80.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.676m	1.049ms	4	5	80.00
V2	scramble	flash_ctrl_wo	3.780m	3.238ms	20	20	100.00
		flash_ctrl_write_word_sweep	15.870s	44.637us	1	1	100.00
		flash_ctrl_read_word_sweep	17.860s	524.046us	1	1	100.00
		flash_ctrl_ro	2.565m	1.229ms	20	20	100.00
		flash_ctrl_rw	11.873m	7.726ms	19	20	95.00
V2	filesystem_support	flash_ctrl_fs_sup	42.230s	2.992ms	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	16.463m	47.829ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.799m	10.012ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.830s	102.941us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	15.100s	52.277us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	20.220s	86.729us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	20.220s	86.729us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	39.870s	79.128us	5	5	100.00
		flash_ctrl_csr_rw	18.510s	67.152us	20	20	100.00
		flash_ctrl_csr_aliasing	1.095m	3.397ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.150s	789.555us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	39.870s	79.128us	5	5	100.00
		flash_ctrl_csr_rw	18.510s	67.152us	20	20	100.00
		flash_ctrl_csr_aliasing	1.095m	3.397ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.150s	789.555us	20	20	100.00
V2		TOTAL			995	1013	98.22
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.430s	14.854us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.430s	14.854us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.430s	14.854us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.430s	14.854us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.510s	25.352us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.330h	2.648ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.347m	3.218ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.347m	3.218ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.347m	3.218ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	32.230s	63.816us	3	3	100.00
		flash_ctrl_wr_intg	15.470s	45.414us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.607m	106.838us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.299m	42.721us	80	80	100.00
		flash_ctrl_disable	22.860s	44.741us	50	50	100.00
		flash_ctrl_sec_info_access	1.506m	8.078ms	50	50	100.00
		flash_ctrl_connect	17.400s	37.081us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.660s	23.553us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	18.510s	67.152us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.430s	14.854us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	18.510s	67.152us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.430s	14.854us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	18.510s	67.152us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.430s	14.854us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.860s	44.741us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	32.230s	63.816us	3	3	100.00
		flash_ctrl_access_after_disable	13.910s	12.431us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.860s	44.741us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	30.770s	508.190us	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	11.873m	7.726ms	19	20	95.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	12.114m	8.921ms	6	10	60.00
		flash_ctrl_rw_derr	13.805m	18.894ms	8	10	80.00
		flash_ctrl_integrity	11.984m	3.293ms	1	5	20.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	35.249m	448.458ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.330h	2.648ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.330h	2.648ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.330h	2.648ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.330h	2.648ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	19.570s	636.509us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.380s	15.298us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	16.140s	74.192us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.330h	2.648ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.330h	2.648ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.330h	2.648ms	5	5	100.00
V2S		TOTAL			144	144	100.00
V3	asymmetric_read_path	flash_ctrl_rd_ooo	43.730s	159.574us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1260	1278	98.59

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	45	81.82
V2S	12	12	12	100.00
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.86	95.25	93.63	97.22	92.52	97.08	97.09	98.21

Failure Buckets

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 5 failures:

Test flash_ctrl_integrity has 2 failures.

0.flash_ctrl_integrity.11812113768167941507824277841495038147660262743711689387428493257953069293279
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_integrity/latest/run.log

  UVM_ERROR @ 5547295.7 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (40298065633171701664048 [0x88890010111402a8930] vs 40882598031721033107458 [0x8a84005409008200802])
  UVM_INFO @ 5547295.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.flash_ctrl_integrity.2181452554121223870693030144951488825075627318949941628099337910555549619887
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_integrity/latest/run.log

  UVM_ERROR @ 3649298.3 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (1349044278785185677625 [0x4921c0100320080139] vs 37797428171092802013227 [0x80100b016407102082b])
  UVM_INFO @ 3649298.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_rw_derr has 1 failures.

1.flash_ctrl_rw_derr.67683051488561092501236334354076932721520170498392063352722768674029359255252
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_derr/latest/run.log

  UVM_ERROR @ 1166822.6 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (595916444805697774088 [0x204e008140094a2208] vs 595916444805697775112 [0x204e008140094a2608])
  UVM_INFO @ 1166822.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_rw_serr has 2 failures.

5.flash_ctrl_rw_serr.71280790898636835106310970262603759223324204296693020328118923095958595053002
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 6295099.5 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (369007502156427247896 [0x140102002030094118] vs 369007502156426723608 [0x140102002030014118])
  UVM_INFO @ 6295099.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.flash_ctrl_rw_serr.74311545386641282611908927518084378293075542962221809479789586514160503320905
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 9408288.9 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (6432185419726690845092 [0x15cb0812010004201a4] vs 6432185419726825062820 [0x15cb0812010084201a4])
  UVM_INFO @ 9408288.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 4 failures:

Test flash_ctrl_serr_address has 1 failures.

0.flash_ctrl_serr_address.108656083899696469382341569598304832438151637261471407563830181747484501313034
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_serr_address/latest/run.log

  UVM_ERROR @ 238606.0 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 238606.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_serr_counter has 1 failures.

1.flash_ctrl_serr_counter.9233297024112013659948938680109828404962879476623479771454834894279977032876
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_serr_counter/latest/run.log

  UVM_ERROR @ 9793385.3 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 9793385.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_rw_serr has 2 failures.

3.flash_ctrl_rw_serr.92014081044666138789741552700661999795732038871366499620316055033297004798067
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 8921395.7 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 8921395.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.flash_ctrl_rw_serr.19174275259468629730782941922584421561657954201179471334966400856767011262584
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 2692777.7 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 2692777.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:289) m_otf_scb [process_read] unexpected double bit error * has 3 failures:
- Test flash_ctrl_integrity has 2 failures.
  - 1.flash_ctrl_integrity.15737003544308195212376208804176358792759722069679475581659624862874902190010
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_integrity/latest/run.log
```
  UVM_ERROR @ 3292547.5 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00004e08
  UVM_INFO @ 3292547.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.flash_ctrl_integrity.106338822452759700397035958865623383872811887640494854222104556618419776320971
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_integrity/latest/run.log
```
  UVM_ERROR @ 581805.3 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00003a00
  UVM_INFO @ 581805.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_rw_derr has 1 failures.
  - 9.flash_ctrl_rw_derr.113189320042194442292932543267031441808303365283957844933689264688025626933646
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 6407364.0 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x000c0000
  UVM_INFO @ 6407364.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 2 failures:
- Test flash_ctrl_intr_wr_slow_flash has 1 failures.
  - 4.flash_ctrl_intr_wr_slow_flash.23635069039837824405236123466247031259375298525252111558000024570651874300517
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_intr_wr_slow_flash/latest/run.log
```
  Job ID: smart:af84cecf-8e74-4eaa-9211-e1da83ddc3e6
```
- Test flash_ctrl_rw has 1 failures.
  - 10.flash_ctrl_rw.4598346011302867027140893363358069444465101481074746588164236437085713891676
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_rw/latest/run.log
```
  Job ID: smart:06a515e8-f0e0-461b-95e5-fac6f547bfd1
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 2 failures:
- Test flash_ctrl_rw_evict_all_en has 2 failures.
  - 21.flash_ctrl_rw_evict_all_en.28821209943665197434500787043081055181193748014753133742193268664087912364087
    Line 292, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/21.flash_ctrl_rw_evict_all_en/latest/run.log
```
  UVM_ERROR @ 8497.9 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 8497.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 26.flash_ctrl_rw_evict_all_en.107457346814506574792651329724634588071500963525809125902422791671437297959022
    Line 291, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/26.flash_ctrl_rw_evict_all_en/latest/run.log
```
  UVM_ERROR @ 25869.0 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 25869.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_otf_item.sv:247) [rd_scr] ecc error is detected has 1 failures:
- Test flash_ctrl_oversize_error has 1 failures.
  - 0.flash_ctrl_oversize_error.47113124616951000401348788609841991147973734786866734859143658531151355462644
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_oversize_error/latest/run.log
```
  UVM_ERROR @ 166880.8 ns: (flash_otf_item.sv:247) [rd_scr] ecc error is detected
  UVM_INFO @ 166880.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp a0b7841c_92de8a93:ffffffff_ffffffff mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 35.flash_ctrl_intr_rd.42914293183275678783189348972955710771469186559196567623162776110504595046417
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/35.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 582697.0 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    2: obs:exp    a0b7841c_92de8a93:ffffffff_ffffffff  mismatch!!
  UVM_INFO @ 582697.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```