FLASH_CTRL Simulation Results

Saturday June 29 2024 23:02:35 UTC

GitHub Revision: `b33f0bcb4a`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 9407974028806500767465982655187958599819354731549473124644158596869486113221

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	4.192m	1.351ms	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	27.830s	20.246us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	47.010s	79.521us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	18.440s	371.060us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.431m	4.654ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.200m	3.477ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	20.000s	101.695us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	18.440s	371.060us	20	20	100.00
		flash_ctrl_csr_aliasing	1.200m	3.477ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	14.000s	19.335us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	14.250s	88.470us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	28.440s	117.150us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	2.106m	127.544us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	37.798m	381.092ms	3	3	100.00
		flash_ctrl_hw_rma_reset	20.601m	290.267ms	20	20	100.00
		flash_ctrl_lcmgr_intg	14.070s	48.911us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	47.680m	248.106ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	8.043m	22.502ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	3.953m	5.506ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.346h	195.650ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.022m	1.471ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	32.560s	101.827us	38	40	95.00
		flash_ctrl_rw_evict_all_en	33.140s	38.424us	38	40	95.00
		flash_ctrl_re_evict	36.890s	172.605us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	8.808m	5.513ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	8.808m	5.513ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	20.363m	36.245ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	29.000s	1.755ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	19.964m	468.110us	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	44.865m	33.320ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	18.601m	861.785us	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	54.526m	1.016ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	13.990s	26.974us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	4.036m	16.474ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	23.470s	61.301us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.920s	19.985us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	18.230m	1.158ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.061m	24.408ms	50	50	100.00
		flash_ctrl_otp_reset	2.282m	42.279us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	37.798m	381.092ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	4.374m	20.165ms	37	40	92.50
		flash_ctrl_intr_wr	1.509m	11.071ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	10.698m	174.089ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	4.369m	98.345ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.632m	1.943ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.317m	12.844ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	28.680s	303.034us	5	5	100.00
		flash_ctrl_ro_derr	3.022m	6.484ms	10	10	100.00
		flash_ctrl_rw_derr	11.850m	5.149ms	6	10	60.00
		flash_ctrl_derr_detect	1.804m	117.988us	4	5	80.00
		flash_ctrl_integrity	12.863m	28.817ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	27.840s	81.687us	5	5	100.00
		flash_ctrl_ro_serr	2.948m	2.636ms	10	10	100.00
		flash_ctrl_rw_serr	12.196m	16.522ms	9	10	90.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.659m	3.319ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.861m	1.098ms	5	5	100.00
V2	scramble	flash_ctrl_wo	3.669m	10.326ms	18	20	90.00
		flash_ctrl_write_word_sweep	15.300s	149.220us	1	1	100.00
		flash_ctrl_read_word_sweep	18.060s	313.427us	1	1	100.00
		flash_ctrl_ro	2.490m	1.093ms	20	20	100.00
		flash_ctrl_rw	12.188m	8.626ms	19	20	95.00
V2	filesystem_support	flash_ctrl_fs_sup	43.980s	367.737us	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	18.629m	60.363ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.605m	10.013ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	15.080s	50.443us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.520s	108.345us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	20.360s	59.469us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	20.360s	59.469us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	47.010s	79.521us	5	5	100.00
		flash_ctrl_csr_rw	18.440s	371.060us	20	20	100.00
		flash_ctrl_csr_aliasing	1.200m	3.477ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.770s	190.295us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	47.010s	79.521us	5	5	100.00
		flash_ctrl_csr_rw	18.440s	371.060us	20	20	100.00
		flash_ctrl_csr_aliasing	1.200m	3.477ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.770s	190.295us	20	20	100.00
V2		TOTAL			997	1013	98.42
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.570s	12.199us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.570s	12.199us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.570s	12.199us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.570s	12.199us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.720s	24.985us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.406h	1.778ms	5	5	100.00
		flash_ctrl_tl_intg_err	16.285m	3.157ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	16.285m	3.157ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	16.285m	3.157ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	32.870s	71.194us	3	3	100.00
		flash_ctrl_wr_intg	15.390s	209.021us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	4.192m	1.351ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.282m	42.279us	80	80	100.00
		flash_ctrl_disable	23.470s	61.301us	50	50	100.00
		flash_ctrl_sec_info_access	1.433m	7.961ms	50	50	100.00
		flash_ctrl_connect	16.920s	19.985us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.240s	39.904us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	18.440s	371.060us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.570s	12.199us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	18.440s	371.060us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.570s	12.199us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	18.440s	371.060us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.570s	12.199us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	23.470s	61.301us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	32.870s	71.194us	3	3	100.00
		flash_ctrl_access_after_disable	14.030s	20.969us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	23.470s	61.301us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	29.000s	1.755ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	12.188m	8.626ms	19	20	95.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	12.196m	16.522ms	9	10	90.00
		flash_ctrl_rw_derr	11.850m	5.149ms	6	10	60.00
		flash_ctrl_integrity	12.863m	28.817ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	37.798m	381.092ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.406h	1.778ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.406h	1.778ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.406h	1.778ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.406h	1.778ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	26.890s	895.280us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.980s	44.321us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.620s	16.069us	4	5	80.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.406h	1.778ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.406h	1.778ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.406h	1.778ms	5	5	100.00
V2S		TOTAL			143	144	99.31
V3	asymmetric_read_path	flash_ctrl_rd_ooo	45.610s	1.026ms	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1261	1278	98.67

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	47	85.45
V2S	12	12	11	91.67
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.32	95.71	94.00	98.31	92.52	98.25	97.28	98.15

Failure Buckets

UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 3 failures:

Test flash_ctrl_rw_serr has 1 failures.

0.flash_ctrl_rw_serr.2625778243849234339349495477869403852657135482795061167682058294309359870912
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 3741964.2 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 3741964.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_derr_detect has 1 failures.

0.flash_ctrl_derr_detect.4075540665414671174230920851240419448804680706727429288234828783003849325059
Line 314, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_derr_detect/latest/run.log

  UVM_ERROR @ 231654.3 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 231654.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_rw has 1 failures.

18.flash_ctrl_rw.69393829793346714718548582815670901062577263615018295120532940202260974122843
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/18.flash_ctrl_rw/latest/run.log

  UVM_ERROR @ 1375740.8 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 1375740.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 3 failures:
- Test flash_ctrl_rw_evict_all_en has 2 failures.
  - 9.flash_ctrl_rw_evict_all_en.36235578586910454640136578327155947869622510271290243246799898554193586819189
    Line 297, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_rw_evict_all_en/latest/run.log
```
  UVM_ERROR @ 24276.7 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 24276.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 37.flash_ctrl_rw_evict_all_en.85197219550178815070871775063789127751998031618183063364386361088498885393783
    Line 290, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/37.flash_ctrl_rw_evict_all_en/latest/run.log
```
  UVM_ERROR @ 14886.3 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 14886.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_rw_evict has 1 failures.
  - 35.flash_ctrl_rw_evict.52625457745659449279606779485569973657275163574146344525578844566282982800743
    Line 288, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/35.flash_ctrl_rw_evict/latest/run.log
```
  UVM_ERROR @ 10657.7 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 10657.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:289) m_otf_scb [process_read] unexpected double bit error * has 2 failures:
- Test flash_ctrl_rw_derr has 2 failures.
  - 1.flash_ctrl_rw_derr.7610725742127942747388374363761156913180620818121139563108099324454143560986
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 11299877.9 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00003ea0
  UVM_INFO @ 11299877.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.flash_ctrl_rw_derr.12830122604620016705148649796193566147073738442735201615515322283550221536376
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 265156.9 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00003e40
  UVM_INFO @ 265156.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 2 failures:

Test flash_ctrl_rw_derr has 2 failures.

5.flash_ctrl_rw_derr.16495231139023891104268856900052186821489062491428051302139354656981231263857
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_rw_derr/latest/run.log

  UVM_ERROR @ 4196046.2 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (74477228255378170010 [0x4099444804180609a] vs 74477228255378161818 [0x4099444804180409a])
  UVM_INFO @ 4196046.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.flash_ctrl_rw_derr.109460187939708766073638578188358582591753270042197450460706924711872569890618
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_rw_derr/latest/run.log

  UVM_ERROR @ 1452764.4 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (1332201947430100402493 [0x48380414e116c0013d] vs 1332490177806252114237 [0x483c0414e116c0013d])
  UVM_INFO @ 1452764.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 2 failures:
- Test flash_ctrl_wo has 2 failures.
  - 7.flash_ctrl_wo.33560137237547165606468021604228901558393770451600837525945408631224468918453
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_wo/latest/run.log
```
  Job ID: smart:9bc1f28f-9826-4c85-85fe-6ce026385d2e
```
  - 8.flash_ctrl_wo.40200290698183093863156696946760198512976182835798075754287317416927306970224
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_wo/latest/run.log
```
  Job ID: smart:7435a17c-c2dd-4bc9-910f-08c0d11784e9
```
UVM_ERROR (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (*) != exp (*) has 1 failures:
- Test flash_ctrl_phy_ack_consistency has 1 failures.
  - 0.flash_ctrl_phy_ack_consistency.99440768821001740722307192524148094278398209314316973712097097096410636244581
    Line 284, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_phy_ack_consistency/latest/run.log
```
  UVM_ERROR @ 20379.2 ns: (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (0x2a) != exp (0x48)
  UVM_INFO @ 20379.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *da2b98_404dde01:ffffffff_404dde* mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 1.flash_ctrl_intr_rd.72413661548079946921987136891995919150250255860918129912769262609718586846414
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 2707617.2 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    1: obs:exp    17da2b98_404dde01:ffffffff_404dde01  mismatch!!
  UVM_INFO @ 2707617.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 1 failures:
- Test flash_ctrl_rw_evict has 1 failures.
  - 2.flash_ctrl_rw_evict.28154167470778652524363222045593224706876180498092294940617698485777462934253
    Line 292, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rw_evict/latest/run.log
```
  UVM_FATAL @ 28811.3 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00001748
  UVM_INFO @ 28811.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *a9bc063_9443d9b0:ffffffff_9443d9b* mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 29.flash_ctrl_intr_rd.63041101148665764354064378457288047194410876342356029145828459964511061860991
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/29.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 4936881.6 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    5: obs:exp    7a9bc063_9443d9b0:ffffffff_9443d9b0  mismatch!!
  UVM_INFO @ 4936881.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *d8670e6_d01e7639:ffffffff_d01e* mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 39.flash_ctrl_intr_rd.100685641229176312451331790197257801535930936011107328048939133206026714217164
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/39.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 1685706.3 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    6: obs:exp    6d8670e6_d01e7639:ffffffff_d01e7639  mismatch!!
  UVM_INFO @ 1685706.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```