FLASH_CTRL Simulation Results

Sunday June 30 2024 23:02:20 UTC

GitHub Revision: `b33f0bcb4a`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 105302396297609026156504164956156290718642058150905320202190590799028860124396

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	4.165m	840.622us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.890s	23.494us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	31.260s	118.479us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	18.150s	139.098us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.451m	13.544ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.332m	15.439ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	20.420s	258.886us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	18.150s	139.098us	20	20	100.00
		flash_ctrl_csr_aliasing	1.332m	15.439ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	14.160s	13.919us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	14.650s	17.475us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	28.160s	54.161us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	1.906m	155.699us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	34.993m	340.555ms	2	3	66.67
		flash_ctrl_hw_rma_reset	16.291m	110.155ms	20	20	100.00
		flash_ctrl_lcmgr_intg	14.480s	24.700us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	43.360m	248.331ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	9.172m	13.939ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	3.033m	2.182ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.143h	77.280ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.553m	2.410ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	33.870s	133.130us	38	40	95.00
		flash_ctrl_rw_evict_all_en	32.200s	104.148us	40	40	100.00
		flash_ctrl_re_evict	37.030s	78.218us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	8.527m	14.660ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	8.527m	14.660ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	15.946m	11.474ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	30.850s	1.868ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	23.883m	5.988ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	43.021m	21.205ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	15.367m	2.599ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	46.985m	933.557us	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	14.530s	17.801us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.429m	4.403ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	23.230s	17.149us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	17.320s	13.849us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	20.216m	905.669us	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.725m	7.486ms	50	50	100.00
		flash_ctrl_otp_reset	2.289m	79.871us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	34.993m	340.555ms	2	3	66.67
V2	interrupts	flash_ctrl_intr_rd	5.274m	7.014ms	36	40	90.00
		flash_ctrl_intr_wr	1.438m	15.101ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	8.288m	12.509ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	4.166m	213.589ms	9	10	90.00
V2	invalid_op	flash_ctrl_invalid_op	1.661m	1.942ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.306m	1.931ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	28.980s	111.820us	5	5	100.00
		flash_ctrl_ro_derr	3.035m	2.356ms	10	10	100.00
		flash_ctrl_rw_derr	12.689m	50.714ms	8	10	80.00
		flash_ctrl_derr_detect	1.786m	128.112us	5	5	100.00
		flash_ctrl_integrity	12.555m	3.393ms	2	5	40.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	28.620s	164.657us	5	5	100.00
		flash_ctrl_ro_serr	3.075m	1.247ms	10	10	100.00
		flash_ctrl_rw_serr	13.746m	56.761ms	6	10	60.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.530m	1.010ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.494m	6.177ms	5	5	100.00
V2	scramble	flash_ctrl_wo	3.808m	2.783ms	20	20	100.00
		flash_ctrl_write_word_sweep	15.570s	141.500us	1	1	100.00
		flash_ctrl_read_word_sweep	17.750s	311.145us	1	1	100.00
		flash_ctrl_ro	2.279m	1.053ms	20	20	100.00
		flash_ctrl_rw	11.888m	8.178ms	19	20	95.00
V2	filesystem_support	flash_ctrl_fs_sup	43.580s	700.049us	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	18.142m	197.247ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.182m	10.012ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.750s	520.815us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.500s	46.479us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	21.250s	109.846us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	21.250s	109.846us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	31.260s	118.479us	5	5	100.00
		flash_ctrl_csr_rw	18.150s	139.098us	20	20	100.00
		flash_ctrl_csr_aliasing	1.332m	15.439ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.440s	391.470us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	31.260s	118.479us	5	5	100.00
		flash_ctrl_csr_rw	18.150s	139.098us	20	20	100.00
		flash_ctrl_csr_aliasing	1.332m	15.439ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.440s	391.470us	20	20	100.00
V2		TOTAL			995	1013	98.22
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.620s	24.680us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.620s	24.680us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.620s	24.680us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.620s	24.680us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.290s	88.325us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.361h	18.452ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.693m	16.944ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.693m	16.944ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.693m	16.944ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	31.900s	88.460us	3	3	100.00
		flash_ctrl_wr_intg	15.640s	84.833us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	4.165m	840.622us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.289m	79.871us	80	80	100.00
		flash_ctrl_disable	23.230s	17.149us	50	50	100.00
		flash_ctrl_sec_info_access	1.574m	2.939ms	50	50	100.00
		flash_ctrl_connect	17.320s	13.849us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.470s	22.916us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	18.150s	139.098us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.620s	24.680us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	18.150s	139.098us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.620s	24.680us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	18.150s	139.098us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.620s	24.680us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	23.230s	17.149us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	31.900s	88.460us	3	3	100.00
		flash_ctrl_access_after_disable	13.990s	19.117us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	23.230s	17.149us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	30.850s	1.868ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	11.888m	8.178ms	19	20	95.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	13.746m	56.761ms	6	10	60.00
		flash_ctrl_rw_derr	12.689m	50.714ms	8	10	80.00
		flash_ctrl_integrity	12.555m	3.393ms	2	5	40.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	34.993m	340.555ms	2	3	66.67
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.361h	18.452ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.361h	18.452ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.361h	18.452ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.361h	18.452ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	20.800s	718.159us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	15.020s	15.280us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	15.260s	62.617us	4	5	80.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.361h	18.452ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.361h	18.452ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.361h	18.452ms	5	5	100.00
V2S		TOTAL			143	144	99.31
V3	asymmetric_read_path	flash_ctrl_rd_ooo	43.180s	57.667us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1259	1278	98.51

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	47	85.45
V2S	12	12	11	91.67
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.28	95.68	93.95	98.31	92.52	98.17	97.09	98.21

Failure Buckets

Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 4 failures:
- Test flash_ctrl_integrity has 1 failures.
  - 0.flash_ctrl_integrity.45510948992776796289249415698622467105233583675781110032570396536972435024150
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_integrity/latest/run.log
```
  Job ID: smart:0a9f08e4-b7f6-428a-b070-2d8c541b62a2
```
- Test flash_ctrl_rw_derr has 1 failures.
  - 2.flash_ctrl_rw_derr.1097488708055340265522706112485506204398713220687208450584345507600869616641
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rw_derr/latest/run.log
```
  Job ID: smart:51d91d72-400c-4b4b-8486-de6743a172db
```
- Test flash_ctrl_intr_wr_slow_flash has 1 failures.
  - 5.flash_ctrl_intr_wr_slow_flash.112573860117538860576606825498577154349188701448825519834978355341143224893407
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_intr_wr_slow_flash/latest/run.log
```
  Job ID: smart:d1f22ef9-77f5-4ed5-9347-8f59a82239f7
```
- Test flash_ctrl_rw has 1 failures.
  - 17.flash_ctrl_rw.3787878803701793036395254184899314424111089244389814941079214639054939405383
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/17.flash_ctrl_rw/latest/run.log
```
  Job ID: smart:a578dff3-b373-4ffd-9bc9-ac1d56ebb3bc
```
UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 3 failures:
- Test flash_ctrl_rw_serr has 3 failures.
  - 1.flash_ctrl_rw_serr.79296222958918741542817320415986484225036942226412970223013738043485883317651
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_serr/latest/run.log
```
  UVM_ERROR @ 304052.4 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 304052.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.flash_ctrl_rw_serr.45086675222571736007440087161272287549003426629944084002920374960386903744844
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rw_serr/latest/run.log
```
  UVM_ERROR @ 12423842.7 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 12423842.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:289) m_otf_scb [process_read] unexpected double bit error * has 2 failures:
- Test flash_ctrl_integrity has 1 failures.
  - 2.flash_ctrl_integrity.65778298140233032998534660943781651375327912066482755497733012174194126678141
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_integrity/latest/run.log
```
  UVM_ERROR @ 1157430.3 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00003410
  UVM_INFO @ 1157430.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_rw_derr has 1 failures.
  - 8.flash_ctrl_rw_derr.93961630421558172661305759538402585868109096635320326812194119070683295791199
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 22898722.2 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00004a08
  UVM_INFO @ 22898722.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (*) != exp (*) has 1 failures:
- Test flash_ctrl_phy_ack_consistency has 1 failures.
  - 0.flash_ctrl_phy_ack_consistency.53777240740222554523884495285483395584360304439533725419433954662188963765505
    Line 284, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_phy_ack_consistency/latest/run.log
```
  UVM_ERROR @ 4931.1 ns: (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (0x2a) != exp (0x69)
  UVM_INFO @ 4931.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '$fell(src_ack_o)' has 1 failures:
- Test flash_ctrl_hw_rma has 1 failures.
  - 1.flash_ctrl_hw_rma.102811052662622362505425770930317176183465094030718231239234608763782586052318
    Line 351, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_hw_rma/latest/run.log
```
      Offending '$fell(src_ack_o)'
  UVM_ERROR @ 110307985.9 ns: (prim_sync_reqack.sv:349) [ASSERT FAILED] SyncReqAckHoldReq
  UVM_INFO @ 110307985.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 1 failures:
- Test flash_ctrl_rw_serr has 1 failures.
  - 3.flash_ctrl_rw_serr.113584881110055509308503587846812247821188780054445030655833138469770137716578
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_rw_serr/latest/run.log
```
  UVM_ERROR @ 1645964.0 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (47387643283737801786482 [0xa08e3a88010a5020472] vs 47387643283737801788530 [0xa08e3a88010a5020c72])
  UVM_INFO @ 1645964.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 1 failures:
- Test flash_ctrl_rw_evict has 1 failures.
  - 3.flash_ctrl_rw_evict.6294308532573708561526516555005092726895676283210003968557659695894467985402
    Line 292, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_rw_evict/latest/run.log
```
  UVM_ERROR @ 110574.0 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 110574.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 1 failures:
- Test flash_ctrl_integrity has 1 failures.
  - 4.flash_ctrl_integrity.72703203089323599929864058070379518449063063593292127005631036023804753036886
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_integrity/latest/run.log
```
  UVM_ERROR @ 17145129.1 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (40828958822603254663682 [0x8a557a080100e0c0a02] vs 2471182748227773399122 [0x85f68cc0a036000052])
  UVM_INFO @ 17145129.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp f960816b_ff237cc3:ffffffff_ff237cc* mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 5.flash_ctrl_intr_rd.106823340959835948301004392781746715950394727940399330151430583557884939427350
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 1429160.3 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    3: obs:exp    f960816b_ff237cc3:ffffffff_ff237cc3  mismatch!!
  UVM_INFO @ 1429160.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *d5_a2501f08:ffffffff_ffffffff mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 19.flash_ctrl_intr_rd.46819295488327195571527341736806924003785121200111976612038585111216408068381
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/19.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 1339107.4 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    4: obs:exp    120885d5_a2501f08:ffffffff_ffffffff  mismatch!!
  UVM_INFO @ 1339107.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *dbc3261_09dfc5de:ffffffff_ffffffff mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 22.flash_ctrl_intr_rd.53191935964936347027227099817124273843778514684657575464238526691472873219757
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/22.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 651477.7 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    2: obs:exp    6dbc3261_09dfc5de:ffffffff_ffffffff  mismatch!!
  UVM_INFO @ 651477.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: * has 1 failures:
- Test flash_ctrl_rw_evict has 1 failures.
  - 30.flash_ctrl_rw_evict.45795667130930345877320614374313729137326290919397035723463623677293881049965
    Line 300, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/30.flash_ctrl_rw_evict/latest/run.log
```
  UVM_ERROR @ 121762.7 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: 0x0
  UVM_INFO @ 121762.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *e95ab10_8d1f7761:ffffffff_ffffffff mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 36.flash_ctrl_intr_rd.44850561870319153167862141073760685312692216222510583610247635644408730335404
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/36.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 3830053.2 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    5: obs:exp    8e95ab10_8d1f7761:ffffffff_ffffffff  mismatch!!
  UVM_INFO @ 3830053.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

FLASH_CTRL Simulation Results

Sunday June 30 2024 23:02:20 UTC

GitHub Revision: b33f0bcb4a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 105302396297609026156504164956156290718642058150905320202190590799028860124396

Test Results

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GitHub Revision: `b33f0bcb4a`