FLASH_CTRL Simulation Results

Monday July 01 2024 17:07:21 UTC

GitHub Revision: `eb56ef55d0`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 287373712151371957859909226915296476629077008125381265920192201371239303276

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.319m	28.106us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	27.960s	82.067us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	47.020s	54.027us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	18.150s	197.108us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.248m	6.330ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.272m	6.766ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	19.880s	94.359us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	18.150s	197.108us	20	20	100.00
		flash_ctrl_csr_aliasing	1.272m	6.766ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.720s	30.611us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	14.040s	16.986us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	28.830s	27.942us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	2.184m	68.320us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	35.774m	804.247ms	3	3	100.00
		flash_ctrl_hw_rma_reset	17.752m	180.206ms	20	20	100.00
		flash_ctrl_lcmgr_intg	14.870s	17.555us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	43.370m	248.085ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	10.492m	5.365ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	3.919m	15.946ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.140h	244.556ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.745m	719.369us	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	33.970s	50.214us	38	40	95.00
		flash_ctrl_rw_evict_all_en	36.370s	70.494us	39	40	97.50
		flash_ctrl_re_evict	38.280s	351.889us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	9.157m	2.842ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	9.157m	2.842ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	17.065m	13.576ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	30.420s	1.366ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	20.585m	3.232ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	43.620m	11.374ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	18.137m	1.808ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	47.481m	1.320ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	14.990s	15.553us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	5.033m	7.362ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	23.790s	13.215us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	18.330s	25.767us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	23.963m	3.941ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.479m	64.426ms	50	50	100.00
		flash_ctrl_otp_reset	2.340m	77.547us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	35.774m	804.247ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	4.940m	3.321ms	39	40	97.50
		flash_ctrl_intr_wr	1.483m	5.204ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	8.002m	43.471ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	5.527m	106.693ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.713m	6.106ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.341m	1.241ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	29.240s	78.040us	5	5	100.00
		flash_ctrl_ro_derr	3.467m	2.918ms	10	10	100.00
		flash_ctrl_rw_derr	14.057m	4.328ms	7	10	70.00
		flash_ctrl_derr_detect	1.988m	197.877us	5	5	100.00
		flash_ctrl_integrity	16.550m	9.525ms	2	5	40.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	30.150s	331.122us	5	5	100.00
		flash_ctrl_ro_serr	2.990m	12.993ms	10	10	100.00
		flash_ctrl_rw_serr	12.445m	9.468ms	4	10	40.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.346m	2.950ms	4	5	80.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.600m	1.800ms	4	5	80.00
V2	scramble	flash_ctrl_wo	4.857m	4.811ms	17	20	85.00
		flash_ctrl_write_word_sweep	16.490s	436.536us	1	1	100.00
		flash_ctrl_read_word_sweep	19.880s	79.366us	1	1	100.00
		flash_ctrl_ro	2.772m	5.135ms	20	20	100.00
		flash_ctrl_rw	12.613m	4.374ms	17	20	85.00
V2	filesystem_support	flash_ctrl_fs_sup	45.880s	654.824us	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	16.835m	281.016ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	6.522m	10.012ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	15.240s	226.700us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.510s	17.986us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	21.340s	495.243us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	21.340s	495.243us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	47.020s	54.027us	5	5	100.00
		flash_ctrl_csr_rw	18.150s	197.108us	20	20	100.00
		flash_ctrl_csr_aliasing	1.272m	6.766ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.220s	1.962ms	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	47.020s	54.027us	5	5	100.00
		flash_ctrl_csr_rw	18.150s	197.108us	20	20	100.00
		flash_ctrl_csr_aliasing	1.272m	6.766ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.220s	1.962ms	20	20	100.00
V2		TOTAL			989	1013	97.63
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.570s	14.319us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.570s	14.319us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.570s	14.319us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.570s	14.319us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.650s	13.789us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.341h	1.518ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.260m	8.351ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.260m	8.351ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.260m	8.351ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	35.420s	416.863us	3	3	100.00
		flash_ctrl_wr_intg	15.810s	99.208us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.319m	28.106us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.340m	77.547us	80	80	100.00
		flash_ctrl_disable	23.790s	13.215us	50	50	100.00
		flash_ctrl_sec_info_access	1.677m	25.920ms	50	50	100.00
		flash_ctrl_connect	18.330s	25.767us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	15.270s	63.856us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	18.150s	197.108us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.570s	14.319us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	18.150s	197.108us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.570s	14.319us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	18.150s	197.108us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.570s	14.319us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	23.790s	13.215us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	35.420s	416.863us	3	3	100.00
		flash_ctrl_access_after_disable	14.760s	24.301us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	23.790s	13.215us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	30.420s	1.366ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	12.613m	4.374ms	17	20	85.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	12.445m	9.468ms	4	10	40.00
		flash_ctrl_rw_derr	14.057m	4.328ms	7	10	70.00
		flash_ctrl_integrity	16.550m	9.525ms	2	5	40.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	35.774m	804.247ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.341h	1.518ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.341h	1.518ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.341h	1.518ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.341h	1.518ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	22.220s	866.633us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.930s	31.394us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	15.210s	16.074us	4	5	80.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.341h	1.518ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.341h	1.518ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.341h	1.518ms	5	5	100.00
V2S		TOTAL			143	144	99.31
V3	asymmetric_read_path	flash_ctrl_rd_ooo	45.780s	89.553us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1253	1278	98.04

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	45	81.82
V2S	12	12	11	91.67
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.16	95.71	93.93	98.31	91.84	98.25	96.89	98.15

Failure Buckets

Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 7 failures:
- Test flash_ctrl_rw has 2 failures.
  - 3.flash_ctrl_rw.88474433829921272892220538889991475784666494158601598974247424773072630048708
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_rw/latest/run.log
```
  Job ID: smart:56903e2a-aaad-401f-906d-7cb7a90f2cda
```
  - 13.flash_ctrl_rw.68438574848161424853754278105955233029257888536435170936516539302005208313054
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_rw/latest/run.log
```
  Job ID: smart:c2a62281-a62b-4712-87fb-130d5b23ea90
```
- Test flash_ctrl_integrity has 1 failures.
  - 3.flash_ctrl_integrity.14244786284682218896831759449976081981263122296038622572817713622509701042026
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_integrity/latest/run.log
```
  Job ID: smart:c79ae5e2-a4f1-4b8a-8a4e-bac44ead834f
```
- Test flash_ctrl_wo has 3 failures.
  - 7.flash_ctrl_wo.1242333706958225907868538718266164282523461333217532964014126436570485536661
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_wo/latest/run.log
```
  Job ID: smart:22ad2606-6a04-42d9-87b7-020c58860d90
```
  - 10.flash_ctrl_wo.33014353140970506617319132715852171019889936634563341993539934464490815899187
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_wo/latest/run.log
```
  Job ID: smart:e7870bae-7217-45ec-8112-47f000c511c0
```
  - ... and 1 more failures.
- Test flash_ctrl_rw_serr has 1 failures.
  - 7.flash_ctrl_rw_serr.32182254637813445141613547418087933846387452480105988378742357082781688642963
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_rw_serr/latest/run.log
```
  Job ID: smart:475af550-c039-4190-99f6-661282c7fee3
```

UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 5 failures:

Test flash_ctrl_serr_counter has 1 failures.

0.flash_ctrl_serr_counter.26185064147175056471335484165602192148502279430810843944825971807187512427302
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_serr_counter/latest/run.log

  UVM_ERROR @ 536308.8 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 536308.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_serr_address has 1 failures.

0.flash_ctrl_serr_address.98467950722062753995837257046774187720873614439497033213682682208357042808445
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_serr_address/latest/run.log

  UVM_ERROR @ 206113.3 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 206113.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_rw_serr has 2 failures.

3.flash_ctrl_rw_serr.18761036633972297259101196702081776392755009164276925484497270130493762856837
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 4117200.1 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 4117200.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.flash_ctrl_rw_serr.67025989620623389980027967743112917402193482482026544429878502034130864836677
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 3107623.0 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 3107623.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_rw has 1 failures.

17.flash_ctrl_rw.6103340632076206828623021422890324574426191103093880163697979181620201439842
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/17.flash_ctrl_rw/latest/run.log

  UVM_ERROR @ 5329287.7 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 5329287.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 3 failures:

Test flash_ctrl_integrity has 1 failures.

2.flash_ctrl_integrity.85627338236801467961647949036318523685707744933969116441035896905849321953979
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_integrity/latest/run.log

  UVM_ERROR @ 5996717.6 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (59127160621373227278859 [0xc854a3054041008220b] vs 37797531729581955875110 [0x8010220002620800126])
  UVM_INFO @ 5996717.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_rw_serr has 2 failures.

6.flash_ctrl_rw_serr.66897820107985033743969970209866132858084300562536419471079596354220672985717
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 5465407.5 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (7397176902253678193216 [0x191007390ad42e86a40] vs 7397176902253678193152 [0x191007390ad42e86a00])
  UVM_INFO @ 5465407.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.flash_ctrl_rw_serr.2652474296834025148255519842851901660998995110298116847424072462547217599021
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 13671598.8 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (18916848998191982505748 [0x4017c0432181920ef14] vs 18916848998209162374932 [0x4017c04321c1920ef14])
  UVM_INFO @ 13671598.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:289) m_otf_scb [process_read] unexpected double bit error * has 3 failures:
- Test flash_ctrl_integrity has 1 failures.
  - 4.flash_ctrl_integrity.53025299903146967704870148549369665418867284334003475385951581482734846174601
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_integrity/latest/run.log
```
  UVM_ERROR @ 593370.8 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00002a08
  UVM_INFO @ 593370.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_rw_derr has 2 failures.
  - 7.flash_ctrl_rw_derr.65554263848069516637529919365991833243337857910070398774799722814624658970566
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 7705407.4 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00000208
  UVM_INFO @ 7705407.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.flash_ctrl_rw_derr.70556478111747337096947368142990004405393471820091403490192208362016530035445
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 2225615.5 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00002600
  UVM_INFO @ 2225615.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 2 failures:

Test flash_ctrl_rw_serr has 1 failures.

1.flash_ctrl_rw_serr.23764831564195228810626434054462642259716566028194411894011531100998083862838
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 3885202.0 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (39651323762217433706720 [0x86580a850050f8030e0] vs 39061027951858728055008 [0x84580a850050f8030e0])
  UVM_INFO @ 3885202.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_rw_derr has 1 failures.

4.flash_ctrl_rw_derr.40438379913563686726518547717607015923448635704676394632681995255761828516572
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw_derr/latest/run.log

  UVM_ERROR @ 11362596.6 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (4723242829400044027904 [0x1000c296886bc914000] vs 4723242829400044027912 [0x1000c296886bc914008])
  UVM_INFO @ 11362596.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (*) != exp (*) has 1 failures:
- Test flash_ctrl_phy_ack_consistency has 1 failures.
  - 1.flash_ctrl_phy_ack_consistency.48158389659676723282749005877942086863744670427926337223431274793772867853544
    Line 284, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_phy_ack_consistency/latest/run.log
```
  UVM_ERROR @ 20865.7 ns: (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (0x2a) != exp (0x5a)
  UVM_INFO @ 20865.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 1 failures:
- Test flash_ctrl_rw_evict has 1 failures.
  - 7.flash_ctrl_rw_evict.104591864030312278736697443377351085138782995271960133785474410579898160890560
    Line 298, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_rw_evict/latest/run.log
```
  UVM_FATAL @ 45617.5 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00001318
  UVM_INFO @ 45617.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 1 failures:
- Test flash_ctrl_rw_evict_all_en has 1 failures.
  - 17.flash_ctrl_rw_evict_all_en.70025775600898976263167481411997162468826861386872448321265322277936300527190
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/17.flash_ctrl_rw_evict_all_en/latest/run.log
```
  UVM_ERROR @ 200159.0 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 200159.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp e739f569_fbaa65c0:ffffffff_ffffffff mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 20.flash_ctrl_intr_rd.1562163356604440133212358917885538628183423932269366141998906726334146111471
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/20.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 2504609.6 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    7: obs:exp    e739f569_fbaa65c0:ffffffff_ffffffff  mismatch!!
  UVM_INFO @ 2504609.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: * has 1 failures:
- Test flash_ctrl_rw_evict has 1 failures.
  - 27.flash_ctrl_rw_evict.60696339290751334613783120646409152171335956754343841879175623972485978651001
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/27.flash_ctrl_rw_evict/latest/run.log
```
  UVM_ERROR @ 53403.5 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: 0x0
  UVM_INFO @ 53403.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```