FLASH_CTRL Simulation Results

Monday July 01 2024 23:02:26 UTC

GitHub Revision: `e9ae10fb42`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 81071883735317974084005537723499931298658500385730214730015283368929474034200

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.708m	389.456us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	27.150s	18.202us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	46.440s	25.771us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	18.050s	46.752us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.251m	2.476ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	56.190s	881.834us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	20.220s	73.155us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	18.050s	46.752us	20	20	100.00
		flash_ctrl_csr_aliasing	56.190s	881.834us	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	14.410s	15.072us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	14.020s	278.317us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	27.680s	38.225us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	1.869m	237.188us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	33.700m	804.166ms	3	3	100.00
		flash_ctrl_hw_rma_reset	19.287m	260.243ms	20	20	100.00
		flash_ctrl_lcmgr_intg	14.360s	48.270us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	50.182m	272.537ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	7.651m	11.224ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	4.055m	12.322ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.267h	349.212ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	3.478m	1.386ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	32.710s	30.613us	38	40	95.00
		flash_ctrl_rw_evict_all_en	31.910s	43.864us	37	40	92.50
		flash_ctrl_re_evict	37.960s	136.432us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	9.419m	1.399ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	9.419m	1.399ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	18.257m	60.460ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	26.020s	1.649ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	25.366m	2.246ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	42.415m	7.616ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	18.562m	1.300ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	44.548m	3.646ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	14.350s	15.257us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.574m	3.457ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.920s	36.315us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	17.140s	47.743us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	10.957m	13.249ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	3.965m	12.297ms	50	50	100.00
		flash_ctrl_otp_reset	2.309m	155.791us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	33.700m	804.166ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	4.713m	11.136ms	38	40	95.00
		flash_ctrl_intr_wr	1.297m	4.764ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	7.927m	12.783ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	3.694m	47.079ms	9	10	90.00
V2	invalid_op	flash_ctrl_invalid_op	1.611m	3.873ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.234m	4.093ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	28.890s	79.583us	5	5	100.00
		flash_ctrl_ro_derr	3.007m	3.089ms	10	10	100.00
		flash_ctrl_rw_derr	13.474m	37.263ms	7	10	70.00
		flash_ctrl_derr_detect	1.802m	124.656us	5	5	100.00
		flash_ctrl_integrity	12.127m	4.978ms	3	5	60.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	28.190s	163.898us	5	5	100.00
		flash_ctrl_ro_serr	3.090m	1.185ms	10	10	100.00
		flash_ctrl_rw_serr	11.531m	17.961ms	7	10	70.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.306m	4.996ms	4	5	80.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.699m	3.947ms	5	5	100.00
V2	scramble	flash_ctrl_wo	3.643m	5.474ms	20	20	100.00
		flash_ctrl_write_word_sweep	15.370s	39.788us	1	1	100.00
		flash_ctrl_read_word_sweep	17.940s	82.770us	1	1	100.00
		flash_ctrl_ro	2.446m	537.797us	20	20	100.00
		flash_ctrl_rw	12.390m	7.164ms	19	20	95.00
V2	filesystem_support	flash_ctrl_fs_sup	39.980s	1.405ms	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	18.208m	62.887ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	2.926m	10.020ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	15.320s	293.638us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.530s	86.759us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	20.780s	212.383us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	20.780s	212.383us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	46.440s	25.771us	5	5	100.00
		flash_ctrl_csr_rw	18.050s	46.752us	20	20	100.00
		flash_ctrl_csr_aliasing	56.190s	881.834us	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.200s	1.684ms	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	46.440s	25.771us	5	5	100.00
		flash_ctrl_csr_rw	18.050s	46.752us	20	20	100.00
		flash_ctrl_csr_aliasing	56.190s	881.834us	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.200s	1.684ms	20	20	100.00
V2		TOTAL			995	1013	98.22
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.280s	29.403us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.280s	29.403us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.280s	29.403us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.280s	29.403us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.590s	22.401us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.395h	9.473ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.325m	897.202us	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.325m	897.202us	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.325m	897.202us	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	32.950s	213.930us	3	3	100.00
		flash_ctrl_wr_intg	15.650s	493.141us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.708m	389.456us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.309m	155.791us	80	80	100.00
		flash_ctrl_disable	22.920s	36.315us	50	50	100.00
		flash_ctrl_sec_info_access	1.593m	13.081ms	50	50	100.00
		flash_ctrl_connect	17.140s	47.743us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.430s	19.340us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	18.050s	46.752us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.280s	29.403us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	18.050s	46.752us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.280s	29.403us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	18.050s	46.752us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.280s	29.403us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.920s	36.315us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	32.950s	213.930us	3	3	100.00
		flash_ctrl_access_after_disable	14.350s	21.397us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.920s	36.315us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	26.020s	1.649ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	12.390m	7.164ms	19	20	95.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	11.531m	17.961ms	7	10	70.00
		flash_ctrl_rw_derr	13.474m	37.263ms	7	10	70.00
		flash_ctrl_integrity	12.127m	4.978ms	3	5	60.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	33.700m	804.166ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.395h	9.473ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.395h	9.473ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.395h	9.473ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.395h	9.473ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	25.480s	795.558us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	15.240s	16.140us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.580s	15.543us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.395h	9.473ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.395h	9.473ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.395h	9.473ms	5	5	100.00
V2S		TOTAL			144	144	100.00
V3	asymmetric_read_path	flash_ctrl_rd_ooo	43.890s	152.900us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1260	1278	98.59

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	46	83.64
V2S	12	12	12	100.00
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.04	95.67	93.72	97.22	92.52	98.04	96.99	98.15

Failure Buckets

Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 3 failures:
- Test flash_ctrl_rw_serr has 1 failures.
  - 0.flash_ctrl_rw_serr.74739157688181201338267676465706786115914242275002709517841370048925790525302
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_serr/latest/run.log
```
  Job ID: smart:31fc126b-16b8-4a8c-b140-c765a89e2277
```
- Test flash_ctrl_intr_wr_slow_flash has 1 failures.
  - 9.flash_ctrl_intr_wr_slow_flash.86710765721724310003247140535826730235388785316888276387338889450941878156753
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_intr_wr_slow_flash/latest/run.log
```
  Job ID: smart:500deebf-7db8-411e-b563-22ec54bc0e97
```
- Test flash_ctrl_rw has 1 failures.
  - 17.flash_ctrl_rw.90564803573607520400722787981067101205061106324375940550823426066074368362337
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/17.flash_ctrl_rw/latest/run.log
```
  Job ID: smart:0d033cbd-ace7-4a2e-b88b-7f4cdda6715e
```

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 3 failures:

Test flash_ctrl_rw_serr has 2 failures.

1.flash_ctrl_rw_serr.13179989288838755731900692050774656267552546172827041253507076141369829943464
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 2743700.2 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (21635438132454086148625 [0x494dc050000c28c0211] vs 21635438132454088245777 [0x494dc050000c2ac0211])
  UVM_INFO @ 2743700.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.flash_ctrl_rw_serr.22285243605340972851316090598533936325917134153919687288351422328394070700857
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 17961040.0 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (9444834446712241193122 [0x20001688868403100a2] vs 9444834451110287704226 [0x20001688c68403100a2])
  UVM_INFO @ 17961040.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_rw_derr has 1 failures.

7.flash_ctrl_rw_derr.100049767382569280940592080785674447199743106282838050291415237947079096162091
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_rw_derr/latest/run.log

  UVM_ERROR @ 3586617.9 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (54413356033642443327496 [0xb85c1024a4824004808] vs 54413355470692489906184 [0xb85c1004a4824004808])
  UVM_INFO @ 3586617.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:289) m_otf_scb [process_read] unexpected double bit error * has 2 failures:
- Test flash_ctrl_integrity has 1 failures.
  - 0.flash_ctrl_integrity.91350769576813136004999836464731017348230404956582531661287263960424698886564
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_integrity/latest/run.log
```
  UVM_ERROR @ 4114739.7 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00004600
  UVM_INFO @ 4114739.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_rw_derr has 1 failures.
  - 4.flash_ctrl_rw_derr.1023164064848566740702101583417116896139773883078569438088391161696430397365
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 3383795.5 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00003b00
  UVM_INFO @ 3383795.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 2 failures:
- Test flash_ctrl_rw_evict_all_en has 2 failures.
  - 11.flash_ctrl_rw_evict_all_en.15401233179086090745183764223322407189365203313674505355868874559644699166751
    Line 295, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/11.flash_ctrl_rw_evict_all_en/latest/run.log
```
  UVM_ERROR @ 33058.5 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 33058.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 29.flash_ctrl_rw_evict_all_en.65670537644481559693554873551897577416251804401978004622906448810198143949584
    Line 302, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/29.flash_ctrl_rw_evict_all_en/latest/run.log
```
  UVM_ERROR @ 48374.7 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 48374.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 2 failures:
- Test flash_ctrl_rw_evict_all_en has 1 failures.
  - 20.flash_ctrl_rw_evict_all_en.85313609279352843492962088743467736366721132341184412498585309443762472758034
    Line 296, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/20.flash_ctrl_rw_evict_all_en/latest/run.log
```
  UVM_FATAL @ 148006.3 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00001840
  UVM_INFO @ 148006.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_rw_evict has 1 failures.
  - 27.flash_ctrl_rw_evict.106997410500689643605151513652374726510458052154944092071686481121198401149346
    Line 292, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/27.flash_ctrl_rw_evict/latest/run.log
```
  UVM_FATAL @ 16227.4 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00001728
  UVM_INFO @ 16227.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 1 failures:
- Test flash_ctrl_serr_counter has 1 failures.
  - 2.flash_ctrl_serr_counter.67523284881247857592352696942642924718752779667615134950046171663377384500601
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_serr_counter/latest/run.log
```
  UVM_ERROR @ 449914.5 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 449914.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp bc0d76d2_9e9b0a73:ffffffff_ffffffff mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 2.flash_ctrl_intr_rd.25294023321146776368963228242471015655380911588128599118738247734199438848094
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 18250504.5 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    2: obs:exp    bc0d76d2_9e9b0a73:ffffffff_ffffffff  mismatch!!
  UVM_INFO @ 18250504.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_scoreboard.sv:481) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@1295402) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test flash_ctrl_rw_derr has 1 failures.

3.flash_ctrl_rw_derr.7622108215856703663289621774340953653916790143748627020865058797235589962476
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_rw_derr/latest/run.log

  UVM_ERROR @ 4938948.4 ns: (cip_base_scoreboard.sv:481) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@1295402) { a_addr: 'h40068  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h22  a_opcode: 'h4  a_user: 'h26d2a  d_param: 'h0  d_source: 'h22  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h1  d_error: 'h1  d_sink: 'h0  d_user: 'heaa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4938948.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 1 failures:
- Test flash_ctrl_integrity has 1 failures.
  - 3.flash_ctrl_integrity.39677980928267560718037633352618852497459282419475891977151015406677220399730
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_integrity/latest/run.log
```
  UVM_ERROR @ 680662.5 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (1037638361921223722018 [0x384020008610c10422] vs 19039139335576904736778 [0x4081d22c0061417200a])
  UVM_INFO @ 680662.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *ad4d714_d6771b8f:ffffffff_d6771b8f mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 13.flash_ctrl_intr_rd.76311401553296376517781754157955101246657176936163544932468768412009022287775
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 1402051.5 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    0: obs:exp    2ad4d714_d6771b8f:ffffffff_d6771b8f  mismatch!!
  UVM_INFO @ 1402051.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: * has 1 failures:
- Test flash_ctrl_rw_evict has 1 failures.
  - 23.flash_ctrl_rw_evict.66257943919001819813628150532459187366887492514909651097456181707582747015561
    Line 291, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/23.flash_ctrl_rw_evict/latest/run.log
```
  UVM_ERROR @ 115245.1 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: 0x0
  UVM_INFO @ 115245.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```