FLASH_CTRL Simulation Results

Saturday July 13 2024 23:02:33 UTC

GitHub Revision: `d51405297e`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 101086804359139103922259090811397817605469534164678958852189348539757618502888

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.371m	1.398ms	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	27.290s	18.331us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	47.160s	24.550us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	18.210s	65.290us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	2.674m	61.502ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.181m	1.718ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	19.670s	235.466us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	18.210s	65.290us	20	20	100.00
		flash_ctrl_csr_aliasing	1.181m	1.718ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.640s	17.131us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.920s	28.501us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.930s	41.105us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	1.880m	64.208us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	34.162m	113.715ms	3	3	100.00
		flash_ctrl_hw_rma_reset	18.739m	420.286ms	20	20	100.00
		flash_ctrl_lcmgr_intg	13.790s	48.035us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	40.175m	348.430ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	6.522m	8.504ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	3.477m	4.480ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.170h	698.424ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.359m	708.179us	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	32.490s	28.029us	38	40	95.00
		flash_ctrl_rw_evict_all_en	32.340s	93.083us	38	40	95.00
		flash_ctrl_re_evict	35.920s	346.258us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	7.686m	3.057ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	7.686m	3.057ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	17.212m	47.453ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	26.500s	1.373ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	19.493m	1.676ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	46.715m	26.121ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	17.349m	1.522ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	54.171m	1.014ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	14.290s	48.961us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.322m	24.706ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.710s	10.705us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	17.180s	16.859us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	22.084m	1.689ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.735m	12.788ms	50	50	100.00
		flash_ctrl_otp_reset	2.293m	100.198us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	34.162m	113.715ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	4.390m	6.081ms	39	40	97.50
		flash_ctrl_intr_wr	1.419m	9.742ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	8.274m	48.919ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	5.266m	169.939ms	9	10	90.00
V2	invalid_op	flash_ctrl_invalid_op	1.717m	3.897ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.309m	11.820ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	23.310s	19.603us	5	5	100.00
		flash_ctrl_ro_derr	2.606m	1.142ms	10	10	100.00
		flash_ctrl_rw_derr	12.717m	20.169ms	7	10	70.00
		flash_ctrl_derr_detect	42.650s	29.617us	0	5	0.00
		flash_ctrl_integrity	13.178m	63.235ms	3	5	60.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	22.620s	76.904us	5	5	100.00
		flash_ctrl_ro_serr	2.599m	2.865ms	10	10	100.00
		flash_ctrl_rw_serr	12.756m	18.675ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.427m	3.693ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.675m	1.988ms	5	5	100.00
V2	scramble	flash_ctrl_wo	4.222m	27.081ms	18	20	90.00
		flash_ctrl_write_word_sweep	14.820s	42.683us	1	1	100.00
		flash_ctrl_read_word_sweep	14.450s	79.314us	1	1	100.00
		flash_ctrl_ro	2.336m	581.025us	20	20	100.00
		flash_ctrl_rw	11.413m	5.181ms	19	20	95.00
V2	filesystem_support	flash_ctrl_fs_sup	41.340s	328.004us	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	16.710m	79.021ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.393m	10.012ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.770s	198.073us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.310s	31.991us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	20.680s	58.948us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	20.680s	58.948us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	47.160s	24.550us	5	5	100.00
		flash_ctrl_csr_rw	18.210s	65.290us	20	20	100.00
		flash_ctrl_csr_aliasing	1.181m	1.718ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.020s	215.308us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	47.160s	24.550us	5	5	100.00
		flash_ctrl_csr_rw	18.210s	65.290us	20	20	100.00
		flash_ctrl_csr_aliasing	1.181m	1.718ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.020s	215.308us	20	20	100.00
V2		TOTAL			994	1013	98.12
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.230s	41.081us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.230s	41.081us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.230s	41.081us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.230s	41.081us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.480s	42.416us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.393h	6.143ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.455m	2.283ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.455m	2.283ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.455m	2.283ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	32.140s	218.155us	3	3	100.00
		flash_ctrl_wr_intg	15.510s	54.194us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.371m	1.398ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.293m	100.198us	80	80	100.00
		flash_ctrl_disable	22.710s	10.705us	50	50	100.00
		flash_ctrl_sec_info_access	1.638m	11.267ms	50	50	100.00
		flash_ctrl_connect	17.180s	16.859us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.100s	42.589us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	18.210s	65.290us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.230s	41.081us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	18.210s	65.290us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.230s	41.081us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	18.210s	65.290us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.230s	41.081us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.710s	10.705us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	32.140s	218.155us	3	3	100.00
		flash_ctrl_access_after_disable	13.860s	39.580us	3	3	100.00
V2S	sec_cm_mem_addr_infection	flash_ctrl_host_addr_infection	30.470s	63.972us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.710s	10.705us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	26.500s	1.373ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	11.413m	5.181ms	19	20	95.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	12.756m	18.675ms	10	10	100.00
		flash_ctrl_rw_derr	12.717m	20.169ms	7	10	70.00
		flash_ctrl_integrity	13.178m	63.235ms	3	5	60.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	34.162m	113.715ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.393h	6.143ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.393h	6.143ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.393h	6.143ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.393h	6.143ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	23.680s	795.955us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.990s	78.225us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	16.670s	58.834us	4	5	80.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.393h	6.143ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.393h	6.143ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.393h	6.143ms	5	5	100.00
V2S		TOTAL			146	147	99.32
V3	asymmetric_read_path	flash_ctrl_rd_ooo	44.380s	155.307us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1261	1281	98.44

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	46	83.64
V2S	13	13	12	92.31
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.26	95.67	94.01	98.31	92.52	98.17	96.89	98.21

Failure Buckets

Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 5 failures:
- Test flash_ctrl_wo has 2 failures.
  - 0.flash_ctrl_wo.80895219936874474931151960380264883846180518923734100570048502963991257951684
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_wo/latest/run.log
```
  Job ID: smart:f769cc8d-f232-4ef9-abaa-37fbb4e6f7f9
```
  - 6.flash_ctrl_wo.95471861191874979226279629844609662307187332339848988322443905574864119493344
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_wo/latest/run.log
```
  Job ID: smart:8429acc5-e126-469e-acd1-a26cff97a6d2
```
- Test flash_ctrl_integrity has 1 failures.
  - 3.flash_ctrl_integrity.53207535694885633342392855005705370657119963451768250798060229831598049471929
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_integrity/latest/run.log
```
  Job ID: smart:0db5e325-1005-406c-a220-5c2213679505
```
- Test flash_ctrl_rw has 1 failures.
  - 4.flash_ctrl_rw.103763788170836390446443738391987389253198343611140219725571844204174469046968
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw/latest/run.log
```
  Job ID: smart:98cbd9d8-eec9-476b-b023-a9558dd1ba89
```
- Test flash_ctrl_intr_wr_slow_flash has 1 failures.
  - 8.flash_ctrl_intr_wr_slow_flash.97715863260586850980416412758009254152271596406829837326440316869363615393054
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_intr_wr_slow_flash/latest/run.log
```
  Job ID: smart:8ab18b75-1711-4630-a9d5-a1cca587ef7e
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:289) m_otf_scb [process_read] unexpected double bit error * has 3 failures:
- Test flash_ctrl_integrity has 1 failures.
  - 0.flash_ctrl_integrity.104028976685262304130059477014366041583311988216612818623576725997134520157746
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_integrity/latest/run.log
```
  UVM_ERROR @ 3557708.3 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00004e10
  UVM_INFO @ 3557708.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_rw_derr has 2 failures.
  - 1.flash_ctrl_rw_derr.3583602483595353241498591400763512746556822398420119187877840306702299259019
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 905719.0 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00004068
  UVM_INFO @ 905719.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.flash_ctrl_rw_derr.83767820146527235957416104542781291880957072406938528070762520070420709667655
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 1140286.8 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00004860
  UVM_INFO @ 1140286.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 3 failures:
- Test flash_ctrl_rw_evict_all_en has 2 failures.
  - 0.flash_ctrl_rw_evict_all_en.15531146819562751304490381369374906747665698327887367437110675473615092011532
    Line 289, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_evict_all_en/latest/run.log
```
  UVM_ERROR @ 10004.3 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 10004.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.flash_ctrl_rw_evict_all_en.66272484037697595540469220412529342358942509447727738612316472719299694790390
    Line 300, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_rw_evict_all_en/latest/run.log
```
  UVM_ERROR @ 46140.6 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 46140.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_rw_evict has 1 failures.
  - 25.flash_ctrl_rw_evict.21265405742082408745638824647521563118088953781602395653392725904052245308864
    Line 292, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/25.flash_ctrl_rw_evict/latest/run.log
```
  UVM_ERROR @ 16654.8 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 16654.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: * has 2 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 2.flash_ctrl_derr_detect.58063905092074222223619254350618428230498883047105497260126033281607019304266
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 29616.8 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: 0x0
  UVM_INFO @ 29616.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_rw_evict has 1 failures.
  - 6.flash_ctrl_rw_evict.75203408857299026395607093847482386102669975418139255864063369257121101980703
    Line 299, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_rw_evict/latest/run.log
```
  UVM_ERROR @ 22196.9 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: 0x0
  UVM_INFO @ 22196.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@157890) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 0.flash_ctrl_derr_detect.83421515052105885596545882481132977471377589441118536936552431513766154641600
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 126256.8 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@157890) { a_addr: 'h69834  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hdf  a_opcode: 'h4  a_user: 'h27f2a  d_param: 'h0  d_source: 'hdf  d_data: 'ha17f7c36  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd27  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 126256.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153260) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 1.flash_ctrl_derr_detect.90669179068019515860261203729618133048058096671938166755930775428736060718166
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 132225.5 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153260) { a_addr: 'h40a70  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hc9  a_opcode: 'h4  a_user: 'h2752a  d_param: 'h0  d_source: 'hc9  d_data: 'h7213e0f5  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd52  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 132225.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (*) != exp (*) has 1 failures:
- Test flash_ctrl_phy_ack_consistency has 1 failures.
  - 2.flash_ctrl_phy_ack_consistency.70701668322780935643703230365766154842929745627694145135975534466048596574225
    Line 284, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_phy_ack_consistency/latest/run.log
```
  UVM_ERROR @ 12682.8 ns: (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (0x2a) != exp (0x40)
  UVM_INFO @ 12682.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154887) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 3.flash_ctrl_derr_detect.20259793826863053698287530609099904556866905593545229781335457595390345239614
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 25489.8 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154887) { a_addr: 'h90b08  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h32  a_opcode: 'h4  a_user: 'h2432a  d_param: 'h0  d_source: 'h32  d_data: 'hd1395e9b  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd10  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 25489.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:552) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 1 failures:
- Test flash_ctrl_rw_derr has 1 failures.
  - 4.flash_ctrl_rw_derr.17303282351172800857120711577165076578829208793939378768787818025346505677626
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 7787442.8 ns: (flash_ctrl_otf_scoreboard.sv:552) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (330032894631627620480 [0x11e420611408168080] vs 1510624515349038925952 [0x51e420611408168880])
  UVM_INFO @ 7787442.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@155632) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 4.flash_ctrl_derr_detect.115175114863878456605332384838593427675098052285202655951161883329077828140888
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 41669.9 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@155632) { a_addr: 'h38a00  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'ha  a_opcode: 'h4  a_user: 'h26eaa  d_param: 'h0  d_source: 'ha  d_data: 'h8fcb47a0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd70  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 41669.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *_b93ba8e0:ffffffff_b93ba8e* mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 9.flash_ctrl_intr_rd.61979295236848052510012315012614316855225237660103897602932494215508140372171
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 1008790.4 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    0: obs:exp    28559659_b93ba8e0:ffffffff_b93ba8e0  mismatch!!
  UVM_INFO @ 1008790.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

FLASH_CTRL Simulation Results

Saturday July 13 2024 23:02:33 UTC

GitHub Revision: d51405297e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 101086804359139103922259090811397817605469534164678958852189348539757618502888

Test Results

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GitHub Revision: `d51405297e`