FLASH_CTRL Simulation Results

Sunday July 14 2024 23:02:31 UTC

GitHub Revision: `c04cc5d074`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 63544391231451201456762274895161998707503467555380647510071702152169450996489

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.670m	148.548us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.710s	24.993us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	46.290s	160.494us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.760s	65.242us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.310m	8.395ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.106m	3.262ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	19.190s	82.180us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.760s	65.242us	20	20	100.00
		flash_ctrl_csr_aliasing	1.106m	3.262ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.810s	219.476us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	14.150s	19.906us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.860s	75.073us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	2.051m	67.199us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	37.884m	423.317ms	3	3	100.00
		flash_ctrl_hw_rma_reset	18.195m	260.226ms	20	20	100.00
		flash_ctrl_lcmgr_intg	14.310s	15.810us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	46.734m	256.367ms	4	5	80.00
V2	erase_suspend	flash_ctrl_erase_suspend	8.238m	5.505ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	3.433m	9.701ms	29	30	96.67
V2	full_memory_access	flash_ctrl_full_mem_access	1.123h	48.913ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.341m	720.488us	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	32.380s	43.086us	39	40	97.50
		flash_ctrl_rw_evict_all_en	32.020s	28.674us	37	40	92.50
		flash_ctrl_re_evict	36.150s	296.375us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	9.678m	5.971ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	9.678m	5.971ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	18.630m	16.043ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	26.690s	411.481us	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	20.067m	1.318ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	42.265m	11.746ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	18.741m	1.636ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	53.127m	1.031ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	14.290s	15.416us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.398m	1.903ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.640s	12.849us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	17.110s	26.781us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	35.347m	1.774ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.493m	6.009ms	50	50	100.00
		flash_ctrl_otp_reset	2.237m	238.015us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	37.884m	423.317ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	4.862m	6.791ms	40	40	100.00
		flash_ctrl_intr_wr	1.417m	2.742ms	9	10	90.00
		flash_ctrl_intr_rd_slow_flash	9.104m	75.791ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	3.738m	27.483ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.571m	4.410ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.218m	965.354us	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	23.670s	19.509us	5	5	100.00
		flash_ctrl_ro_derr	2.984m	6.515ms	10	10	100.00
		flash_ctrl_rw_derr	13.348m	7.904ms	6	10	60.00
		flash_ctrl_derr_detect	43.000s	26.471us	0	5	0.00
		flash_ctrl_integrity	11.242m	15.088ms	3	5	60.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	22.880s	54.624us	5	5	100.00
		flash_ctrl_ro_serr	2.605m	2.799ms	10	10	100.00
		flash_ctrl_rw_serr	12.043m	8.068ms	6	10	60.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.305m	3.105ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.605m	935.861us	5	5	100.00
V2	scramble	flash_ctrl_wo	4.175m	48.024ms	19	20	95.00
		flash_ctrl_write_word_sweep	15.680s	142.653us	1	1	100.00
		flash_ctrl_read_word_sweep	14.130s	38.828us	1	1	100.00
		flash_ctrl_ro	2.207m	564.460us	19	20	95.00
		flash_ctrl_rw	11.480m	7.534ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	40.730s	334.924us	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	16.954m	81.487ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	4.340m	10.014ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	15.020s	295.521us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.670s	30.970us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	19.290s	53.895us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	19.290s	53.895us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	46.290s	160.494us	5	5	100.00
		flash_ctrl_csr_rw	17.760s	65.242us	20	20	100.00
		flash_ctrl_csr_aliasing	1.106m	3.262ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.410s	67.240us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	46.290s	160.494us	5	5	100.00
		flash_ctrl_csr_rw	17.760s	65.242us	20	20	100.00
		flash_ctrl_csr_aliasing	1.106m	3.262ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.410s	67.240us	20	20	100.00
V2		TOTAL			989	1013	97.63
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.410s	13.787us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.410s	13.787us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.410s	13.787us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.410s	13.787us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.640s	26.079us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.342h	1.320ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.296m	1.418ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.296m	1.418ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.296m	1.418ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	32.650s	619.163us	3	3	100.00
		flash_ctrl_wr_intg	15.140s	44.937us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.670m	148.548us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.237m	238.015us	80	80	100.00
		flash_ctrl_disable	22.640s	12.849us	50	50	100.00
		flash_ctrl_sec_info_access	1.968m	35.938ms	50	50	100.00
		flash_ctrl_connect	17.110s	26.781us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	13.960s	326.282us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.760s	65.242us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.410s	13.787us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.760s	65.242us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.410s	13.787us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.760s	65.242us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.410s	13.787us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.640s	12.849us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	32.650s	619.163us	3	3	100.00
		flash_ctrl_access_after_disable	13.990s	44.463us	3	3	100.00
V2S	sec_cm_mem_addr_infection	flash_ctrl_host_addr_infection	30.550s	27.554us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.640s	12.849us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	26.690s	411.481us	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	11.480m	7.534ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	12.043m	8.068ms	6	10	60.00
		flash_ctrl_rw_derr	13.348m	7.904ms	6	10	60.00
		flash_ctrl_integrity	11.242m	15.088ms	3	5	60.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	37.884m	423.317ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.342h	1.320ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.342h	1.320ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.342h	1.320ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.342h	1.320ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	21.870s	891.483us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.060s	23.289us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.270s	34.604us	4	5	80.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.342h	1.320ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.342h	1.320ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.342h	1.320ms	5	5	100.00
V2S		TOTAL			146	147	99.32
V3	asymmetric_read_path	flash_ctrl_rd_ooo	43.960s	51.481us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1256	1281	98.05

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	44	80.00
V2S	13	13	12	92.31
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.18	95.71	94.12	98.31	91.84	98.27	96.89	98.15

Failure Buckets

Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 6 failures:
- Test flash_ctrl_rw_derr has 1 failures.
  - 1.flash_ctrl_rw_derr.28185958251695041609718444917364428356928432326036159174561681082481557818094
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_derr/latest/run.log
```
  Job ID: smart:2af08ecc-4147-45c7-a0c3-05926aa8b162
```
- Test flash_ctrl_rw_serr has 2 failures.
  - 6.flash_ctrl_rw_serr.86956703190167439569838168533217373080456959693847448380903534855404264028825
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_rw_serr/latest/run.log
```
  Job ID: smart:0d83727a-d4e6-4c94-88e1-d18b4a4db567
```
  - 8.flash_ctrl_rw_serr.105967907283289210000723835542710608423902295264348850386218682068711456226377
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_rw_serr/latest/run.log
```
  Job ID: smart:5483d9d0-910a-4670-8029-d5d4f1a7ebf2
```
- Test flash_ctrl_intr_wr has 1 failures.
  - 6.flash_ctrl_intr_wr.39764434617971574321171759872939095873031901966239520541577208411244790818091
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_intr_wr/latest/run.log
```
  Job ID: smart:51dc9e9b-b5c1-4030-8255-f7b7c0d20586
```
- Test flash_ctrl_wo has 1 failures.
  - 10.flash_ctrl_wo.69366758592554091454548350029835293687442008576051389937767195852044775532124
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_wo/latest/run.log
```
  Job ID: smart:dd45127f-3de7-4804-8ce8-3cca010933d2
```
- Test flash_ctrl_prog_reset has 1 failures.
  - 15.flash_ctrl_prog_reset.3311742113141108767523273605035837466821632211862188255551488350543782129827
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/15.flash_ctrl_prog_reset/latest/run.log
```
  Job ID: smart:a4820ffa-1091-4a97-9cb9-e6e5a24f6043
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:289) m_otf_scb [process_read] unexpected double bit error * has 4 failures:
- Test flash_ctrl_rw_derr has 3 failures.
  - 0.flash_ctrl_rw_derr.55768765800687071132457871994275200460032057491632421734176207641672807803816
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 17121439.8 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00004000
  UVM_INFO @ 17121439.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.flash_ctrl_rw_derr.56271433249133862441304297388977761106175481538731198789850621941501697759455
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 7208765.1 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00003e20
  UVM_INFO @ 7208765.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test flash_ctrl_integrity has 1 failures.
  - 4.flash_ctrl_integrity.109271311056900975956863994075780933094424183795899954045046981370514012051073
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_integrity/latest/run.log
```
  UVM_ERROR @ 2384428.7 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00003e00
  UVM_INFO @ 2384428.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 4 failures:
- Test flash_ctrl_rw_evict_all_en has 3 failures.
  - 13.flash_ctrl_rw_evict_all_en.69508726556805269458253273387823267583428170661692852034290178251056286792232
    Line 285, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_rw_evict_all_en/latest/run.log
```
  UVM_ERROR @ 15700.3 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 15700.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 30.flash_ctrl_rw_evict_all_en.15390594387091534931157854203193020051791877779486672455076995889661725580031
    Line 291, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/30.flash_ctrl_rw_evict_all_en/latest/run.log
```
  UVM_ERROR @ 18346.2 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 18346.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test flash_ctrl_rw_evict has 1 failures.
  - 34.flash_ctrl_rw_evict.76204040164201142519572548427343817876265731533301736919108348262016686241283
    Line 296, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/34.flash_ctrl_rw_evict/latest/run.log
```
  UVM_ERROR @ 21069.1 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 21069.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 2 failures:
- Test flash_ctrl_rw_serr has 2 failures.
  - 2.flash_ctrl_rw_serr.111851181239904042161305589500723792807233405852456772390827802762152526232268
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rw_serr/latest/run.log
```
  UVM_ERROR @ 12524412.0 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 12524412.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.flash_ctrl_rw_serr.22813438156388258108098819731868141108061639468498943309965377245007655186715
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_rw_serr/latest/run.log
```
  UVM_ERROR @ 3357699.5 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 3357699.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154980) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 0.flash_ctrl_derr_detect.32838558179211985908722904033949047257492825512489953189577284783242680686557
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 74799.9 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154980) { a_addr: 'h52820  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h8b  a_opcode: 'h4  a_user: 'h24e2a  d_param: 'h0  d_source: 'h8b  d_data: 'hf3ad61de  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd70  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 74799.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (*) != exp (*) has 1 failures:
- Test flash_ctrl_phy_ack_consistency has 1 failures.
  - 0.flash_ctrl_phy_ack_consistency.78480411781077477580180419722891469013338138220766029748513437209418125052017
    Line 284, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_phy_ack_consistency/latest/run.log
```
  UVM_ERROR @ 10577.1 ns: (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (0x2a) != exp (0x74)
  UVM_INFO @ 10577.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_err triggered unexpectedly has 1 failures:
- Test flash_ctrl_ro has 1 failures.
  - 1.flash_ctrl_ro.111075738642537313115238933323629744475396345510442871004491747310162225659206
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_ro/latest/run.log
```
  UVM_ERROR @ 9231.4 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_err triggered unexpectedly
  UVM_INFO @ 9231.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154562) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 1.flash_ctrl_derr_detect.92035965706347521026707740383057785972738358327450736549838698273461920676304
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 26470.8 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154562) { a_addr: 'h35524  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1a  a_opcode: 'h4  a_user: 'h277aa  d_param: 'h0  d_source: 'h1a  d_data: 'h2c9e688  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd16  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 26470.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153730) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 2.flash_ctrl_derr_detect.102159974404409841180885516530001041855959760188503816895728457052598017762771
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 41742.4 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153730) { a_addr: 'h5b4a0  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hbe  a_opcode: 'h4  a_user: 'h25aaa  d_param: 'h0  d_source: 'hbe  d_data: 'h31cb7a20  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd3e  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 41742.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:552) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 1 failures:
- Test flash_ctrl_integrity has 1 failures.
  - 2.flash_ctrl_integrity.109257479398827959688450680834138797162763197940908804885614983317995472296615
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_integrity/latest/run.log
```
  UVM_ERROR @ 509349.8 ns: (flash_ctrl_otf_scoreboard.sv:552) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (11216567446862359988256 [0x2600d24990001208820] vs 2066914814806041084080 [0x700c3489150260c0b0])
  UVM_INFO @ 509349.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test flash_ctrl_host_ctrl_arb has 1 failures.
  - 3.flash_ctrl_host_ctrl_arb.25565958044847494382290500692452993302161576971277204042186335924459155717155
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_host_ctrl_arb/latest/run.log
```
  Job ID: smart:2ed0800c-07cc-4914-8c36-a21383cfc0cd
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@157519) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 3.flash_ctrl_derr_detect.4358281943420560845409158975399403457144857910713284067336890645202276777182
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 81464.7 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@157519) { a_addr: 'hcb590  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hbe  a_opcode: 'h4  a_user: 'h25eaa  d_param: 'h0  d_source: 'hbe  d_data: 'h121e4991  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd52  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 81464.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@156220) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 4.flash_ctrl_derr_detect.17274007143518350660067596463019306970601352655410676342682179264632643612879
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 26295.3 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@156220) { a_addr: 'h42534  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hee  a_opcode: 'h4  a_user: 'h2782a  d_param: 'h0  d_source: 'hee  d_data: 'hebc85507  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd67  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 26295.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

FLASH_CTRL Simulation Results

Sunday July 14 2024 23:02:31 UTC

GitHub Revision: c04cc5d074

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 63544391231451201456762274895161998707503467555380647510071702152169450996489

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `c04cc5d074`