FLASH_CTRL Simulation Results

Monday July 15 2024 23:02:37 UTC

GitHub Revision: `a04e34f557`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 78455839157994684327892029952813991699715169368132023215715425571513813941951

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	4.733m	5.642ms	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	27.080s	49.041us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	46.180s	182.352us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	18.400s	197.388us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.369m	3.456ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.163m	6.529ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	21.180s	167.480us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	18.400s	197.388us	20	20	100.00
		flash_ctrl_csr_aliasing	1.163m	6.529ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.940s	18.290us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	14.220s	17.692us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	27.250s	85.729us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	1.660m	71.603us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	46.374m	879.239ms	3	3	100.00
		flash_ctrl_hw_rma_reset	16.809m	540.444ms	20	20	100.00
		flash_ctrl_lcmgr_intg	14.000s	15.219us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	46.127m	226.948ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	14.543m	66.277ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	3.598m	9.759ms	29	30	96.67
V2	full_memory_access	flash_ctrl_full_mem_access	1.056h	187.821ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	3.082m	5.640ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	31.990s	70.561us	39	40	97.50
		flash_ctrl_rw_evict_all_en	32.180s	62.742us	40	40	100.00
		flash_ctrl_re_evict	35.650s	239.714us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	10.190m	38.256ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	10.190m	38.256ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	14.508m	45.188ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	28.260s	1.541ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	21.929m	953.955us	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	42.144m	5.131ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	16.860m	1.943ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	54.878m	1.838ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	14.110s	69.813us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.711m	5.916ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.890s	19.536us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.810s	16.172us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	31.452m	1.068ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.458m	12.948ms	50	50	100.00
		flash_ctrl_otp_reset	2.258m	142.964us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	46.374m	879.239ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	4.413m	7.433ms	39	40	97.50
		flash_ctrl_intr_wr	1.504m	20.016ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	8.122m	11.844ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	4.234m	220.576ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.656m	5.113ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.212m	958.945us	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	23.370s	34.855us	5	5	100.00
		flash_ctrl_ro_derr	3.160m	1.181ms	10	10	100.00
		flash_ctrl_rw_derr	12.677m	4.503ms	9	10	90.00
		flash_ctrl_derr_detect	1.075m	118.213us	0	5	0.00
		flash_ctrl_integrity	10.674m	9.083ms	3	5	60.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	22.500s	24.817us	5	5	100.00
		flash_ctrl_ro_serr	2.843m	1.154ms	10	10	100.00
		flash_ctrl_rw_serr	10.744m	4.012ms	8	10	80.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.759m	4.518ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	2.002m	4.639ms	5	5	100.00
V2	scramble	flash_ctrl_wo	3.833m	5.587ms	20	20	100.00
		flash_ctrl_write_word_sweep	14.820s	91.283us	1	1	100.00
		flash_ctrl_read_word_sweep	15.080s	42.212us	1	1	100.00
		flash_ctrl_ro	2.547m	11.604ms	20	20	100.00
		flash_ctrl_rw	11.518m	7.244ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	43.960s	1.939ms	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	15.957m	78.993ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.025m	10.012ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	16.710s	610.772us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.370s	15.765us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	20.130s	100.509us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	20.130s	100.509us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	46.180s	182.352us	5	5	100.00
		flash_ctrl_csr_rw	18.400s	197.388us	20	20	100.00
		flash_ctrl_csr_aliasing	1.163m	6.529ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	34.140s	710.923us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	46.180s	182.352us	5	5	100.00
		flash_ctrl_csr_rw	18.400s	197.388us	20	20	100.00
		flash_ctrl_csr_aliasing	1.163m	6.529ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	34.140s	710.923us	20	20	100.00
V2		TOTAL			1000	1013	98.72
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	15.930s	22.567us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	15.930s	22.567us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	15.930s	22.567us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	15.930s	22.567us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.510s	14.826us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.381h	2.116ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.365m	888.921us	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.365m	888.921us	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.365m	888.921us	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	32.280s	358.700us	3	3	100.00
		flash_ctrl_wr_intg	15.250s	325.026us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	4.733m	5.642ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.258m	142.964us	80	80	100.00
		flash_ctrl_disable	22.890s	19.536us	50	50	100.00
		flash_ctrl_sec_info_access	1.721m	29.131ms	50	50	100.00
		flash_ctrl_connect	16.810s	16.172us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.310s	66.396us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	18.400s	197.388us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	15.930s	22.567us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	18.400s	197.388us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	15.930s	22.567us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	18.400s	197.388us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	15.930s	22.567us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.890s	19.536us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	32.280s	358.700us	3	3	100.00
		flash_ctrl_access_after_disable	13.730s	13.345us	3	3	100.00
V2S	sec_cm_mem_addr_infection	flash_ctrl_host_addr_infection	30.780s	27.206us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.890s	19.536us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	28.260s	1.541ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	11.518m	7.244ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	10.744m	4.012ms	8	10	80.00
		flash_ctrl_rw_derr	12.677m	4.503ms	9	10	90.00
		flash_ctrl_integrity	10.674m	9.083ms	3	5	60.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	46.374m	879.239ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.381h	2.116ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.381h	2.116ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.381h	2.116ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.381h	2.116ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	22.010s	755.592us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.230s	24.614us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.550s	55.400us	4	5	80.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.381h	2.116ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.381h	2.116ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.381h	2.116ms	5	5	100.00
V2S		TOTAL			146	147	99.32
V3	asymmetric_read_path	flash_ctrl_rd_ooo	48.080s	299.962us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1267	1281	98.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	48	87.27
V2S	13	13	12	92.31
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.09	95.73	94.02	98.31	91.16	98.27	96.89	98.21

Failure Buckets

Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 3 failures:
- Test flash_ctrl_integrity has 1 failures.
  - 0.flash_ctrl_integrity.3138532902841328546780834255055573188938693849055537677493075200301126300926
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_integrity/latest/run.log
```
  Job ID: smart:523966c6-34d5-49b9-afc5-096722c74d6d
```
- Test flash_ctrl_rw_serr has 1 failures.
  - 8.flash_ctrl_rw_serr.50606021794090181889010932228338708821858947344396408061767123765890300491081
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_rw_serr/latest/run.log
```
  Job ID: smart:80263ac6-35e0-403e-ac6a-bbe584840452
```
- Test flash_ctrl_prog_reset has 1 failures.
  - 23.flash_ctrl_prog_reset.59540171571798650848714396808564293372917048703476802304889751970185661855451
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/23.flash_ctrl_prog_reset/latest/run.log
```
  Job ID: smart:9c556691-5e26-471e-b2cc-6b693b739100
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: * has 2 failures:
- Test flash_ctrl_derr_detect has 2 failures.
  - 3.flash_ctrl_derr_detect.105537086845888866628831665360187756655318905857752962795092487548898705629699
    Line 303, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 118212.7 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: 0x0
  UVM_INFO @ 118212.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.flash_ctrl_derr_detect.88675586984918126525803793421071476394577919276072894916101755778529992331115
    Line 303, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 150170.6 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: 0x0
  UVM_INFO @ 150170.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154429) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 0.flash_ctrl_derr_detect.96961012046055746821361221907465914222722850615010649877669292816241928899531
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 79911.8 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154429) { a_addr: 'ha1508  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h5a  a_opcode: 'h4  a_user: 'h26d2a  d_param: 'h0  d_source: 'h5a  d_data: 'hfc61bdf1  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd38  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 79911.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (*) != exp (*) has 1 failures:
- Test flash_ctrl_phy_ack_consistency has 1 failures.
  - 0.flash_ctrl_phy_ack_consistency.91641019841405801756594821477109912481210459603279734155316398975603413769003
    Line 284, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_phy_ack_consistency/latest/run.log
```
  UVM_ERROR @ 19200.7 ns: (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (0x2a) != exp (0x62)
  UVM_INFO @ 19200.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 1 failures:
- Test flash_ctrl_rw_serr has 1 failures.
  - 1.flash_ctrl_rw_serr.93401911737727992869910294398272904953647932797217170875686139113544514843917
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_serr/latest/run.log
```
  UVM_ERROR @ 2596347.8 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 2596347.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@155874) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 1.flash_ctrl_derr_detect.45508606604780702014802198131687094130100356834893222025853782150321762130139
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 29150.4 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@155874) { a_addr: 'h7b338  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h75  a_opcode: 'h4  a_user: 'h2742a  d_param: 'h0  d_source: 'h75  d_data: 'h49e48d1c  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd52  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 29150.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_scoreboard.sv:481) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@1682668) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test flash_ctrl_rw_derr has 1 failures.

2.flash_ctrl_rw_derr.53158709114031489735192632656018762643991063834463199802129421286897549781366
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rw_derr/latest/run.log

  UVM_ERROR @ 822202.5 ns: (cip_base_scoreboard.sv:481) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@1682668) { a_addr: 'h60084  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h7c  a_opcode: 'h4  a_user: 'h244aa  d_param: 'h0  d_source: 'h7c  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h1  d_error: 'h1  d_sink: 'h0  d_user: 'heaa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 822202.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154607) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 2.flash_ctrl_derr_detect.50011836759743875999253101916195853161180329869047215412108937518601973725251
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 25147.3 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154607) { a_addr: 'hdf0f0  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hc0  a_opcode: 'h4  a_user: 'h276aa  d_param: 'h0  d_source: 'hc0  d_data: 'hce29fe1a  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd01  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 25147.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:552) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 1 failures:
- Test flash_ctrl_integrity has 1 failures.
  - 4.flash_ctrl_integrity.104683767199937710949659806878091206395714108905650548887213787849871172998707
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_integrity/latest/run.log
```
  UVM_ERROR @ 2461559.1 ns: (flash_ctrl_otf_scoreboard.sv:552) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (57871580669373998834212 [0xc413984420530022224] vs 1479828811972398416437 [0x5038c0100513220235])
  UVM_INFO @ 2461559.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 1 failures:
- Test flash_ctrl_rw_evict has 1 failures.
  - 5.flash_ctrl_rw_evict.42191308938224491182295034952718152345699719696466553435371921157873609481462
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_rw_evict/latest/run.log
```
  UVM_ERROR @ 23274.7 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 23274.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp bbced1ad_4bb3c3c4:ffffffff_4bb3c3c* mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 14.flash_ctrl_intr_rd.86185015214325287189766367812082382316496595461089337832918626414258045328845
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/14.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 380349.2 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    1: obs:exp    bbced1ad_4bb3c3c4:ffffffff_4bb3c3c4  mismatch!!
  UVM_INFO @ 380349.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```