FLASH_CTRL Simulation Results

Tuesday July 16 2024 23:15:02 UTC

GitHub Revision: `aad711e1bc`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 38297581588405771015102977205739484163575733999253050480227719508149669635625

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	4.047m	1.361ms	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.410s	17.710us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	46.890s	44.912us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.790s	146.425us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.358m	8.421ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.030m	2.907ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	20.700s	179.322us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.790s	146.425us	20	20	100.00
		flash_ctrl_csr_aliasing	1.030m	2.907ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	14.380s	25.690us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	14.460s	17.321us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.710s	85.053us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	1.711m	508.200us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	36.223m	334.253ms	3	3	100.00
		flash_ctrl_hw_rma_reset	18.545m	320.258ms	20	20	100.00
		flash_ctrl_lcmgr_intg	13.680s	15.809us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	41.529m	230.824ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	7.564m	5.616ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	3.467m	38.900ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.151h	325.734ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.622m	831.283us	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	31.870s	187.961us	37	40	92.50
		flash_ctrl_rw_evict_all_en	31.390s	27.855us	39	40	97.50
		flash_ctrl_re_evict	35.870s	490.006us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	9.135m	40.435ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	9.135m	40.435ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	19.372m	191.639ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	31.540s	1.326ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	22.317m	1.608ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	41.610m	19.994ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	16.023m	792.732us	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	53.056m	9.018ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	13.730s	37.471us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	4.058m	3.938ms	4	5	80.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.550s	26.302us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.560s	15.594us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	20.547m	2.201ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.190m	21.492ms	50	50	100.00
		flash_ctrl_otp_reset	2.265m	39.566us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	36.223m	334.253ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	4.239m	7.096ms	40	40	100.00
		flash_ctrl_intr_wr	1.372m	2.911ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	8.083m	25.519ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	7.208m	265.364ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.718m	19.391ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.236m	5.477ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	23.280s	238.563us	5	5	100.00
		flash_ctrl_ro_derr	2.964m	9.045ms	10	10	100.00
		flash_ctrl_rw_derr	12.418m	16.606ms	8	10	80.00
		flash_ctrl_derr_detect	42.280s	25.704us	0	5	0.00
		flash_ctrl_integrity	12.546m	19.812ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	23.340s	26.808us	5	5	100.00
		flash_ctrl_ro_serr	2.501m	600.256us	10	10	100.00
		flash_ctrl_rw_serr	12.614m	4.325ms	8	10	80.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.040m	850.813us	4	5	80.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.799m	1.120ms	5	5	100.00
V2	scramble	flash_ctrl_wo	3.955m	34.755ms	20	20	100.00
		flash_ctrl_write_word_sweep	15.320s	143.710us	1	1	100.00
		flash_ctrl_read_word_sweep	13.920s	25.026us	1	1	100.00
		flash_ctrl_ro	2.354m	579.635us	18	20	90.00
		flash_ctrl_rw	10.503m	4.499ms	19	20	95.00
V2	filesystem_support	flash_ctrl_fs_sup	43.270s	1.313ms	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	16.509m	157.491ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.493m	10.012ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	15.020s	327.413us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.580s	18.468us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	20.640s	56.822us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	20.640s	56.822us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	46.890s	44.912us	5	5	100.00
		flash_ctrl_csr_rw	17.790s	146.425us	20	20	100.00
		flash_ctrl_csr_aliasing	1.030m	2.907ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.080s	653.805us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	46.890s	44.912us	5	5	100.00
		flash_ctrl_csr_rw	17.790s	146.425us	20	20	100.00
		flash_ctrl_csr_aliasing	1.030m	2.907ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.080s	653.805us	20	20	100.00
V2		TOTAL			995	1013	98.22
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.440s	32.131us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.440s	32.131us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.440s	32.131us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.440s	32.131us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.370s	15.758us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.337h	6.775ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.190m	1.631ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.190m	1.631ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.190m	1.631ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	32.270s	823.091us	3	3	100.00
		flash_ctrl_wr_intg	15.230s	83.302us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	4.047m	1.361ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.265m	39.566us	80	80	100.00
		flash_ctrl_disable	22.550s	26.302us	50	50	100.00
		flash_ctrl_sec_info_access	1.401m	10.262ms	50	50	100.00
		flash_ctrl_connect	16.560s	15.594us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.030s	19.557us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.790s	146.425us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.440s	32.131us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.790s	146.425us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.440s	32.131us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.790s	146.425us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.440s	32.131us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.550s	26.302us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	32.270s	823.091us	3	3	100.00
		flash_ctrl_access_after_disable	13.920s	19.930us	3	3	100.00
V2S	sec_cm_mem_addr_infection	flash_ctrl_host_addr_infection	31.000s	248.866us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.550s	26.302us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	31.540s	1.326ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	10.503m	4.499ms	19	20	95.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	12.614m	4.325ms	8	10	80.00
		flash_ctrl_rw_derr	12.418m	16.606ms	8	10	80.00
		flash_ctrl_integrity	12.546m	19.812ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	36.223m	334.253ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.337h	6.775ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.337h	6.775ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.337h	6.775ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.337h	6.775ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	20.110s	756.663us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.180s	91.103us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	15.010s	45.490us	4	5	80.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.337h	6.775ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.337h	6.775ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.337h	6.775ms	5	5	100.00
V2S		TOTAL			146	147	99.32
V3	asymmetric_read_path	flash_ctrl_rd_ooo	43.750s	106.058us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1262	1281	98.52

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	46	83.64
V2S	13	13	12	92.31
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.15	95.70	93.96	98.31	91.84	98.21	96.89	98.12

Failure Buckets

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 3 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 0.flash_ctrl_derr_detect.71317653012921826091769752618501529977696372884434590339230042565231346965054
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 45993.6 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 45993.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_rw_evict has 1 failures.
  - 0.flash_ctrl_rw_evict.89660751063247398752562092151635227637193813032291648326914385334992853903310
    Line 289, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_evict/latest/run.log
```
  UVM_ERROR @ 41233.5 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 41233.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_rw_evict_all_en has 1 failures.
  - 27.flash_ctrl_rw_evict_all_en.103569675927100127389587285193339531715165309132761432799708698020491055043124
    Line 292, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/27.flash_ctrl_rw_evict_all_en/latest/run.log
```
  UVM_ERROR @ 26462.9 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 26462.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 3 failures:
- Test flash_ctrl_rw_serr has 1 failures.
  - 1.flash_ctrl_rw_serr.35569287248507161268023222340993532768723750764045302581882836880195817217399
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_serr/latest/run.log
```
  Job ID: smart:320fd4b1-7ece-469b-b8d5-6fc16c281988
```
- Test flash_ctrl_rw_derr has 1 failures.
  - 4.flash_ctrl_rw_derr.100035346379305403719111589366520333939563362406700571452360853063046552780014
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw_derr/latest/run.log
```
  Job ID: smart:35114829-30c7-46a0-b1fb-9c8a0296383b
```
- Test flash_ctrl_rw has 1 failures.
  - 13.flash_ctrl_rw.88746511547482873660287867994002159818138769211636089513661188047809751701701
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_rw/latest/run.log
```
  Job ID: smart:25e8c9ae-f0fb-4184-b6d7-79237a3a51ef
```
UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 2 failures:
- Test flash_ctrl_serr_counter has 1 failures.
  - 1.flash_ctrl_serr_counter.60938516917112098381377055651028935209003665341875881580588663756011962579128
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_serr_counter/latest/run.log
```
  UVM_ERROR @ 275069.0 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 275069.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_ro has 1 failures.
  - 17.flash_ctrl_ro.4333981121511455385579520745033995352785886886621379396225523266418159139469
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/17.flash_ctrl_ro/latest/run.log
```
  UVM_ERROR @ 436855.7 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 436855.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 2 failures:
- Test flash_ctrl_rw_evict has 2 failures.
  - 3.flash_ctrl_rw_evict.72346117705808506731748327726461489223350803722604414970023257204572787572702
    Line 298, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_rw_evict/latest/run.log
```
  UVM_FATAL @ 8626.6 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00000af8
  UVM_INFO @ 8626.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 20.flash_ctrl_rw_evict.22013101835678747819017090864023727172360529226231676020922219213255753735500
    Line 289, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/20.flash_ctrl_rw_evict/latest/run.log
```
  UVM_FATAL @ 28602.5 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00000bf8
  UVM_INFO @ 28602.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:289) m_otf_scb [process_read] unexpected double bit error * has 1 failures:
- Test flash_ctrl_rw_derr has 1 failures.
  - 0.flash_ctrl_rw_derr.77280814239240180951781032975867059191666887355402975846159562057420623720575
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 4364458.8 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00004000
  UVM_INFO @ 4364458.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_otf_item.sv:247) [rd_scr] ecc error is detected has 1 failures:
- Test flash_ctrl_oversize_error has 1 failures.
  - 0.flash_ctrl_oversize_error.22933781469973242358957096331545644915871700816280238705232768890623167235050
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_oversize_error/latest/run.log
```
  UVM_ERROR @ 7273952.3 ns: (flash_otf_item.sv:247) [rd_scr] ecc error is detected
  UVM_INFO @ 7273952.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153790) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 1.flash_ctrl_derr_detect.51705599945314366760189551875615122657050376787075610771432519940026206843628
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 37331.1 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153790) { a_addr: 'ha0c34  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h55  a_opcode: 'h4  a_user: 'h2602a  d_param: 'h0  d_source: 'h55  d_data: 'hf309db61  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd60  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 37331.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_scoreboard.sv:481) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@79208) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test flash_ctrl_derr_detect has 1 failures.

2.flash_ctrl_derr_detect.83629195654890281246807371240512457901407352953323475466967647161201573331890
Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_derr_detect/latest/run.log

  UVM_ERROR @ 42797.9 ns: (cip_base_scoreboard.sv:481) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@79208) { a_addr: 'he78b0  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h4c  a_opcode: 'h4  a_user: 'h27c2a  d_param: 'h0  d_source: 'h4c  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h1  d_error: 'h1  d_sink: 'h0  d_user: 'heaa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 42797.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153205) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 3.flash_ctrl_derr_detect.85766239475327286317428522215250639673904331244981754519502745190253345827090
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 25703.7 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153205) { a_addr: 'h6f0d0  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h8d  a_opcode: 'h4  a_user: 'h2602a  d_param: 'h0  d_source: 'h8d  d_data: 'h6b92e62a  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd6d  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 25703.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_scoreboard.sv:481) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@2413979) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test flash_ctrl_rw_serr has 1 failures.

4.flash_ctrl_rw_serr.40865476063638122827220353279820278921292314098439908975756510597233287749683
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 1336746.0 ns: (cip_base_scoreboard.sv:481) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@2413979) { a_addr: 'h401f0  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hf  a_opcode: 'h4  a_user: 'h26aaa  d_param: 'h0  d_source: 'hf  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h1  d_error: 'h1  d_sink: 'h0  d_user: 'heaa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 1336746.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154464) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 4.flash_ctrl_derr_detect.86586960680902627210429752049330164187530572111974059238138344959301369352653
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 96179.7 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154464) { a_addr: 'h59518  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h79  a_opcode: 'h4  a_user: 'h250aa  d_param: 'h0  d_source: 'h79  d_data: 'he035f00  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd6f  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 96179.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (*) != exp (*) has 1 failures:
- Test flash_ctrl_phy_ack_consistency has 1 failures.
  - 4.flash_ctrl_phy_ack_consistency.45995324090700632493694728170075012287243006604191824154197831144615989327584
    Line 284, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_phy_ack_consistency/latest/run.log
```
  UVM_ERROR @ 19974.3 ns: (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (0x2a) != exp (0x3b)
  UVM_INFO @ 19974.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_err triggered unexpectedly has 1 failures:
- Test flash_ctrl_ro has 1 failures.
  - 5.flash_ctrl_ro.31561854255890855968748726521331448471538075047408379370845875425049209099002
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_ro/latest/run.log
```
  UVM_ERROR @ 131394.6 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_err triggered unexpectedly
  UVM_INFO @ 131394.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```