FLASH_CTRL Simulation Results

Wednesday July 17 2024 23:02:16 UTC

GitHub Revision: `8b2da8db5e`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 31877364624131593519988921539075110140045739991215723614576185349550879231344

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.695m	27.230us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	27.180s	26.067us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	47.240s	111.900us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	19.160s	476.100us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.328m	2.281ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	53.920s	1.566ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	21.370s	155.035us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	19.160s	476.100us	20	20	100.00
		flash_ctrl_csr_aliasing	53.920s	1.566ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.900s	14.307us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	14.450s	22.218us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	27.170s	55.032us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	2.031m	134.610us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	36.106m	554.080ms	3	3	100.00
		flash_ctrl_hw_rma_reset	16.558m	160.171ms	20	20	100.00
		flash_ctrl_lcmgr_intg	14.030s	15.853us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	42.649m	244.185ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	6.955m	17.055ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	3.621m	12.612ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.115h	129.132ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.239m	5.513ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	32.650s	108.317us	39	40	97.50
		flash_ctrl_rw_evict_all_en	31.880s	132.443us	39	40	97.50
		flash_ctrl_re_evict	36.870s	81.381us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	8.533m	5.560ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	8.533m	5.560ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	21.729m	29.122ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	27.880s	1.312ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	28.183m	2.309ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	43.704m	7.009ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	14.957m	371.630us	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	45.396m	518.563us	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	14.320s	65.643us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	4.344m	14.668ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.850s	29.788us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.870s	15.228us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	18.900m	724.312us	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.451m	11.121ms	50	50	100.00
		flash_ctrl_otp_reset	2.263m	36.159us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	36.106m	554.080ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	4.226m	1.798ms	37	40	92.50
		flash_ctrl_intr_wr	1.402m	10.288ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	8.648m	52.944ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	3.480m	101.514ms	9	10	90.00
V2	invalid_op	flash_ctrl_invalid_op	1.576m	1.005ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.322m	3.967ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	23.120s	19.704us	5	5	100.00
		flash_ctrl_ro_derr	3.083m	1.325ms	10	10	100.00
		flash_ctrl_rw_derr	12.559m	9.063ms	9	10	90.00
		flash_ctrl_derr_detect	43.300s	27.043us	0	5	0.00
		flash_ctrl_integrity	11.841m	27.677ms	2	5	40.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	23.240s	25.873us	5	5	100.00
		flash_ctrl_ro_serr	2.802m	1.442ms	10	10	100.00
		flash_ctrl_rw_serr	11.344m	17.239ms	6	10	60.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.654m	1.805ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.860m	7.873ms	5	5	100.00
V2	scramble	flash_ctrl_wo	3.867m	11.067ms	20	20	100.00
		flash_ctrl_write_word_sweep	15.580s	75.532us	1	1	100.00
		flash_ctrl_read_word_sweep	14.880s	22.293us	1	1	100.00
		flash_ctrl_ro	2.413m	3.997ms	20	20	100.00
		flash_ctrl_rw	11.024m	8.266ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	42.930s	1.924ms	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	16.553m	151.261ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.244m	10.013ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.400s	39.651us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.490s	17.802us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	20.860s	63.779us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	20.860s	63.779us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	47.240s	111.900us	5	5	100.00
		flash_ctrl_csr_rw	19.160s	476.100us	20	20	100.00
		flash_ctrl_csr_aliasing	53.920s	1.566ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	34.980s	305.264us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	47.240s	111.900us	5	5	100.00
		flash_ctrl_csr_rw	19.160s	476.100us	20	20	100.00
		flash_ctrl_csr_aliasing	53.920s	1.566ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	34.980s	305.264us	20	20	100.00
V2		TOTAL			994	1013	98.12
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.250s	12.906us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.250s	12.906us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.250s	12.906us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.250s	12.906us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.410s	14.813us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.332h	11.593ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.307m	3.015ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.307m	3.015ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.307m	3.015ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	32.330s	289.201us	3	3	100.00
		flash_ctrl_wr_intg	15.200s	155.993us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.695m	27.230us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.263m	36.159us	80	80	100.00
		flash_ctrl_disable	22.850s	29.788us	50	50	100.00
		flash_ctrl_sec_info_access	1.519m	17.429ms	50	50	100.00
		flash_ctrl_connect	16.870s	15.228us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.320s	23.391us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	19.160s	476.100us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.250s	12.906us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	19.160s	476.100us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.250s	12.906us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	19.160s	476.100us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.250s	12.906us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.850s	29.788us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	32.330s	289.201us	3	3	100.00
		flash_ctrl_access_after_disable	13.960s	172.530us	3	3	100.00
V2S	sec_cm_mem_addr_infection	flash_ctrl_host_addr_infection	30.060s	170.323us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.850s	29.788us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	27.880s	1.312ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	11.024m	8.266ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	11.344m	17.239ms	6	10	60.00
		flash_ctrl_rw_derr	12.559m	9.063ms	9	10	90.00
		flash_ctrl_integrity	11.841m	27.677ms	2	5	40.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	36.106m	554.080ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.332h	11.593ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.332h	11.593ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.332h	11.593ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.332h	11.593ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	23.200s	756.138us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.610s	45.315us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.390s	25.564us	4	5	80.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.332h	11.593ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.332h	11.593ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.332h	11.593ms	5	5	100.00
V2S		TOTAL			146	147	99.32
V3	asymmetric_read_path	flash_ctrl_rd_ooo	45.550s	58.577us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1261	1281	98.44

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	47	85.45
V2S	13	13	12	92.31
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.04	95.24	93.95	98.31	92.52	97.16	96.89	98.21

Failure Buckets

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:289) m_otf_scb [process_read] unexpected double bit error * has 2 failures:
- Test flash_ctrl_integrity has 1 failures.
  - 1.flash_ctrl_integrity.84656797410453882400032283020781430578145210498704264689840033457341727360919
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_integrity/latest/run.log
```
  UVM_ERROR @ 1874177.6 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00003400
  UVM_INFO @ 1874177.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_rw_derr has 1 failures.
  - 4.flash_ctrl_rw_derr.27042874685997351211118213934173235437367658765809507875201768148816713330005
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 17032628.0 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00003810
  UVM_INFO @ 17032628.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 2 failures:
- Test flash_ctrl_rw_serr has 2 failures.
  - 2.flash_ctrl_rw_serr.92471034905055032381793310949616711021170531515558193143171514926464685386142
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rw_serr/latest/run.log
```
  UVM_ERROR @ 42544315.1 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 42544315.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.flash_ctrl_rw_serr.52277473361886075551830457843228220902215853910925645917398399074800097514819
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_rw_serr/latest/run.log
```
  UVM_ERROR @ 3021748.2 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 3021748.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 2 failures:
- Test flash_ctrl_rw_evict has 1 failures.
  - 2.flash_ctrl_rw_evict.107239088833421289441669861405420709864272193331773196750155402000021332981387
    Line 294, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rw_evict/latest/run.log
```
  UVM_ERROR @ 30944.2 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 30944.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_rw_evict_all_en has 1 failures.
  - 21.flash_ctrl_rw_evict_all_en.20966236254636365953516606061229184416234288419040880427477495351002550158939
    Line 289, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/21.flash_ctrl_rw_evict_all_en/latest/run.log
```
  UVM_ERROR @ 44733.3 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 44733.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:552) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 2 failures:

Test flash_ctrl_integrity has 2 failures.

3.flash_ctrl_integrity.55039099047715766920207498322604160372796517377804677378872750221893926678454
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_integrity/latest/run.log

  UVM_ERROR @ 2896422.8 ns: (flash_ctrl_otf_scoreboard.sv:552) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (19337398746633557270547 [0x41848510a2239146013] vs 7088162538536221966387 [0x1804004021aa2928033])
  UVM_INFO @ 2896422.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.flash_ctrl_integrity.59140667634733971195482072857292752667148244166148508171838929561133881718336
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_integrity/latest/run.log

  UVM_ERROR @ 2210750.9 ns: (flash_ctrl_otf_scoreboard.sv:552) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (18890044083281456017444 [0x4000806020064a03024] vs 19185443731545732423716 [0x4100b846100e4282024])
  UVM_INFO @ 2210750.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:552) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 2 failures:

Test flash_ctrl_rw_serr has 2 failures.

6.flash_ctrl_rw_serr.99095001729750214132394127744841409907341442894642921104185550283581184027436
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 9441856.2 ns: (flash_ctrl_otf_scoreboard.sv:552) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (49013316527411310642688 [0xa6104681200058c4600] vs 49013316527411310708224 [0xa6104681200058d4600])
  UVM_INFO @ 9441856.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.flash_ctrl_rw_serr.9981563703886404259462306335210700461430381525754971927163391229730271253813
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 4203378.6 ns: (flash_ctrl_otf_scoreboard.sv:552) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (102907840858008064704 [0x594221808000012c0] vs 102908966757914907328 [0x594261808000012c0])
  UVM_INFO @ 4203378.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: * has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 0.flash_ctrl_derr_detect.22736307955916598564471623323081658278572738266068161409117842879808734277248
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 24547.6 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: 0x0
  UVM_INFO @ 24547.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154801) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 1.flash_ctrl_derr_detect.90952494695126929690210274015502854990059089720664491857434500415165547307917
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 27043.2 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154801) { a_addr: 'h8e2a8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h46  a_opcode: 'h4  a_user: 'h24f2a  d_param: 'h0  d_source: 'h46  d_data: 'hb8144e2  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd5f  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 27043.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153780) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 2.flash_ctrl_derr_detect.91740152631287825070561531995704984434715707079474234731981557866656644212911
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 78451.1 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153780) { a_addr: 'h1dbe0  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h50  a_opcode: 'h4  a_user: 'h2702a  d_param: 'h0  d_source: 'h50  d_data: 'h9bb1cf18  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd71  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 78451.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (*) != exp (*) has 1 failures:
- Test flash_ctrl_phy_ack_consistency has 1 failures.
  - 2.flash_ctrl_phy_ack_consistency.78693121335955210152656871138310856002944477787297971334392504556381101827887
    Line 284, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_phy_ack_consistency/latest/run.log
```
  UVM_ERROR @ 20721.0 ns: (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (0x2a) != exp (0x3b)
  UVM_INFO @ 20721.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153270) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 3.flash_ctrl_derr_detect.26623663377005470795184041630512595071691469876015088931776285439640173615248
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 32430.8 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153270) { a_addr: 'h4e224  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hb4  a_opcode: 'h4  a_user: 'h27faa  d_param: 'h0  d_source: 'hb4  d_data: 'h975a6556  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd65  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 32430.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@156404) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 4.flash_ctrl_derr_detect.106945358338902334922214694393278874582050570009112663109135076844950447253492
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 45576.9 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@156404) { a_addr: 'h8cfa4  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hf1  a_opcode: 'h4  a_user: 'h2752a  d_param: 'h0  d_source: 'hf1  d_data: 'hd0e498eb  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd1c  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 45576.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 1 failures:
- Test flash_ctrl_intr_wr_slow_flash has 1 failures.
  - 9.flash_ctrl_intr_wr_slow_flash.54755603747222741043555927509742833201848241562231482666283232305345528686328
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_intr_wr_slow_flash/latest/run.log
```
  Job ID: smart:fbd13b3d-3ddd-425a-96bd-89137267d0c6
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *a761fd9_1020ec76:ffffffff_1020ec* mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 30.flash_ctrl_intr_rd.85734260464078916642966081139192153862281571248788928837498661764695677476066
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/30.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 1755797.4 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    1: obs:exp    2a761fd9_1020ec76:ffffffff_1020ec76  mismatch!!
  UVM_INFO @ 1755797.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp be377f3c_4e9a9cf5:ffffffff_4e9a9cf* mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 33.flash_ctrl_intr_rd.30721768122211973361920974508282443171664890964021645875191679338982316467231
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/33.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 3298091.9 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    6: obs:exp    be377f3c_4e9a9cf5:ffffffff_4e9a9cf5  mismatch!!
  UVM_INFO @ 3298091.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *f4fb_1b3b56bc:ffffffff_ffffffff mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 34.flash_ctrl_intr_rd.103597155860672904590538518908384227016960599668413566033394478305681202593402
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/34.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 2464671.1 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    5: obs:exp    1341f4fb_1b3b56bc:ffffffff_ffffffff  mismatch!!
  UVM_INFO @ 2464671.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```