FLASH_CTRL Simulation Results

Thursday July 18 2024 23:02:12 UTC

GitHub Revision: `974aaab627`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 46057207235241274571178436692064798722168129065126426307050395083305588858879

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	4.722m	878.029us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.590s	15.200us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	45.450s	49.388us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.770s	401.981us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.105m	3.756ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.136m	6.801ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	19.870s	48.295us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.770s	401.981us	20	20	100.00
		flash_ctrl_csr_aliasing	1.136m	6.801ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	14.290s	18.045us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	14.040s	18.084us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	27.460s	45.686us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	2.119m	153.397us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	33.886m	161.649ms	3	3	100.00
		flash_ctrl_hw_rma_reset	19.621m	480.344ms	20	20	100.00
		flash_ctrl_lcmgr_intg	13.940s	15.803us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	40.355m	400.784ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	6.954m	4.093ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	3.593m	4.980ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.208h	195.643ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.630m	736.295us	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	33.650s	74.303us	38	40	95.00
		flash_ctrl_rw_evict_all_en	32.270s	30.362us	40	40	100.00
		flash_ctrl_re_evict	36.670s	113.380us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	9.551m	2.771ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	9.551m	2.771ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	14.925m	46.518ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	27.160s	332.168us	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	22.813m	3.016ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	43.448m	13.132ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	17.791m	6.781ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	42.251m	3.701ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	14.450s	15.760us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	4.029m	1.519ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.770s	15.756us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	17.110s	18.839us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	29.787m	395.378us	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	3.505m	3.485ms	50	50	100.00
		flash_ctrl_otp_reset	2.247m	41.270us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	33.886m	161.649ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	4.857m	1.931ms	40	40	100.00
		flash_ctrl_intr_wr	1.874m	31.070ms	8	10	80.00
		flash_ctrl_intr_rd_slow_flash	7.617m	54.880ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	10.469m	465.030ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.662m	8.107ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.303m	4.954ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	23.820s	56.833us	5	5	100.00
		flash_ctrl_ro_derr	3.054m	2.589ms	10	10	100.00
		flash_ctrl_rw_derr	12.613m	14.558ms	7	10	70.00
		flash_ctrl_derr_detect	42.060s	38.539us	0	5	0.00
		flash_ctrl_integrity	12.273m	4.240ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	22.890s	39.857us	5	5	100.00
		flash_ctrl_ro_serr	2.524m	474.524us	10	10	100.00
		flash_ctrl_rw_serr	12.279m	3.965ms	6	10	60.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.728m	3.912ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.940m	10.708ms	5	5	100.00
V2	scramble	flash_ctrl_wo	5.014m	12.891ms	20	20	100.00
		flash_ctrl_write_word_sweep	15.130s	403.210us	1	1	100.00
		flash_ctrl_read_word_sweep	14.720s	85.770us	1	1	100.00
		flash_ctrl_ro	2.617m	9.846ms	19	20	95.00
		flash_ctrl_rw	11.378m	7.950ms	18	20	90.00
V2	filesystem_support	flash_ctrl_fs_sup	42.190s	637.498us	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	16.043m	42.147ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.927m	10.012ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.890s	172.710us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.880s	15.149us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	20.190s	296.261us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	20.190s	296.261us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	45.450s	49.388us	5	5	100.00
		flash_ctrl_csr_rw	17.770s	401.981us	20	20	100.00
		flash_ctrl_csr_aliasing	1.136m	6.801ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.030s	766.733us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	45.450s	49.388us	5	5	100.00
		flash_ctrl_csr_rw	17.770s	401.981us	20	20	100.00
		flash_ctrl_csr_aliasing	1.136m	6.801ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.030s	766.733us	20	20	100.00
V2		TOTAL			994	1013	98.12
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.040s	28.219us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.040s	28.219us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.040s	28.219us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.040s	28.219us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.550s	20.140us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.347h	2.618ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.187m	1.265ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.187m	1.265ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.187m	1.265ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	32.050s	216.169us	3	3	100.00
		flash_ctrl_wr_intg	15.410s	218.548us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	4.722m	878.029us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.247m	41.270us	80	80	100.00
		flash_ctrl_disable	22.770s	15.756us	50	50	100.00
		flash_ctrl_sec_info_access	1.540m	33.626ms	50	50	100.00
		flash_ctrl_connect	17.110s	18.839us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.310s	38.686us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.770s	401.981us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.040s	28.219us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.770s	401.981us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.040s	28.219us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.770s	401.981us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.040s	28.219us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.770s	15.756us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	32.050s	216.169us	3	3	100.00
		flash_ctrl_access_after_disable	14.120s	22.134us	3	3	100.00
V2S	sec_cm_mem_addr_infection	flash_ctrl_host_addr_infection	30.390s	65.264us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.770s	15.756us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	27.160s	332.168us	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	11.378m	7.950ms	18	20	90.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	12.279m	3.965ms	6	10	60.00
		flash_ctrl_rw_derr	12.613m	14.558ms	7	10	70.00
		flash_ctrl_integrity	12.273m	4.240ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	33.886m	161.649ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.347h	2.618ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.347h	2.618ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.347h	2.618ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.347h	2.618ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	24.590s	885.068us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.440s	24.542us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.180s	22.501us	4	5	80.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.347h	2.618ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.347h	2.618ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.347h	2.618ms	5	5	100.00
V2S		TOTAL			146	147	99.32
V3	asymmetric_read_path	flash_ctrl_rd_ooo	43.560s	58.722us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1261	1281	98.44

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	48	87.27
V2S	13	13	12	92.31
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.28	95.74	94.06	98.31	92.52	98.29	96.89	98.12

Failure Buckets

UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 4 failures:

Test flash_ctrl_ro has 1 failures.

0.flash_ctrl_ro.34055900893874302594974176725450565497207160328878195079423875442294808306365
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_ro/latest/run.log

  UVM_ERROR @ 3387909.6 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 3387909.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_rw_serr has 3 failures.

3.flash_ctrl_rw_serr.4277875124821790220919883033493742359832454799502230628859486129436090334356
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 7341301.5 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 7341301.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.flash_ctrl_rw_serr.79091802216024296335310155426406840068182795977064554873082191259812005893764
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 1193278.9 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 1193278.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 4 failures:
- Test flash_ctrl_rw has 2 failures.
  - 1.flash_ctrl_rw.26691246855775433820524679663710278413970325407159459876104308484417646466251
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw/latest/run.log
```
  Job ID: smart:d25b3747-8f02-43b1-9ecd-6d6642ea20a0
```
  - 4.flash_ctrl_rw.22240727973959716805350031458621221404219910010440062063035094864014845461993
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw/latest/run.log
```
  Job ID: smart:514bc67a-7989-4620-95ac-3b8dec897a11
```
- Test flash_ctrl_intr_wr has 2 failures.
  - 7.flash_ctrl_intr_wr.36237782052232000304487665262243638215715659797677742075598085305796648881163
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_intr_wr/latest/run.log
```
  Job ID: smart:20c02e28-2368-40cc-bbe9-dcba68bd2eee
```
  - 9.flash_ctrl_intr_wr.36942031765669274719148902980492782885168047030915515089725326371936402275801
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_intr_wr/latest/run.log
```
  Job ID: smart:9c03c608-e678-4cd9-aba0-edbd20f2bab3
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:289) m_otf_scb [process_read] unexpected double bit error * has 3 failures:
- Test flash_ctrl_rw_derr has 3 failures.
  - 0.flash_ctrl_rw_derr.7177734462580434991203825663474407523691474398189504411891178692901909550408
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 8085467.3 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00004c00
  UVM_INFO @ 8085467.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.flash_ctrl_rw_derr.103655383673161290975843573432497074664798967626225827055027135336034448677552
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 9201047.4 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00004208
  UVM_INFO @ 9201047.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 2 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 4.flash_ctrl_derr_detect.34746070647971403687591682418766286645278445967558982075183805280729115450416
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 24726.2 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 24726.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_rw_evict has 1 failures.
  - 10.flash_ctrl_rw_evict.1928069726068372133481131171398892073554188391195293837526248344697146328812
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_rw_evict/latest/run.log
```
  UVM_ERROR @ 20642.7 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 20642.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153162) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 0.flash_ctrl_derr_detect.114912714620229632003794726878027340679682667911032317812853114042034988016199
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 67491.1 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153162) { a_addr: 'h650f4  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h64  a_opcode: 'h4  a_user: 'h2782a  d_param: 'h0  d_source: 'h64  d_data: 'he5961019  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd74  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 67491.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:552) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 1 failures:
- Test flash_ctrl_rw_serr has 1 failures.
  - 1.flash_ctrl_rw_serr.52287375454998798960738314041960057974371370626295899524320506836869047890484
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_serr/latest/run.log
```
  UVM_ERROR @ 11367910.2 ns: (flash_ctrl_otf_scoreboard.sv:552) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (1229513627959100800 [0x11101c2161010580] vs 1229513627959100801 [0x11101c2161010581])
  UVM_INFO @ 11367910.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154296) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 1.flash_ctrl_derr_detect.19124597661772127670247547877097366251012052287756050445974918018354468465143
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 24276.1 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154296) { a_addr: 'h9e54c  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hf5  a_opcode: 'h4  a_user: 'h2752a  d_param: 'h0  d_source: 'hf5  d_data: 'ha6ca40d6  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2f  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 24276.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153419) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 2.flash_ctrl_derr_detect.43864667219465756848875496648645370894104359077176234244984137274380038007386
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 40559.7 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153419) { a_addr: 'h7e410  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h4a  a_opcode: 'h4  a_user: 'h24f2a  d_param: 'h0  d_source: 'h4a  d_data: 'hf36bb50c  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd43  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 40559.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153697) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 3.flash_ctrl_derr_detect.92294566416448072301337672957484942944651964162637564888909628540872991562468
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 38539.4 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153697) { a_addr: 'h1b0ec  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h4b  a_opcode: 'h4  a_user: 'h2772a  d_param: 'h0  d_source: 'h4b  d_data: 'hd31f1951  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd79  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 38539.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (*) != exp (*) has 1 failures:
- Test flash_ctrl_phy_ack_consistency has 1 failures.
  - 3.flash_ctrl_phy_ack_consistency.72242275402119960010482212681313183674754649306427686861366490287177805930259
    Line 284, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_phy_ack_consistency/latest/run.log
```
  UVM_ERROR @ 20508.6 ns: (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (0x2a) != exp (0x7d)
  UVM_INFO @ 20508.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: * has 1 failures:
- Test flash_ctrl_rw_evict has 1 failures.
  - 20.flash_ctrl_rw_evict.90170755226151088965105578972772423621716903066701711221614074344307526784486
    Line 295, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/20.flash_ctrl_rw_evict/latest/run.log
```
  UVM_ERROR @ 44146.5 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: 0x0
  UVM_INFO @ 44146.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```