FLASH_CTRL Simulation Results

Friday July 19 2024 23:02:26 UTC

GitHub Revision: `e971cd9798`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 26138077499038500271813583950138268511494909685260487774440110801232111361107

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.693m	70.296us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	25.960s	16.704us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	46.830s	25.214us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.870s	262.709us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.256m	3.280ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.131m	3.361ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	21.170s	46.309us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.870s	262.709us	20	20	100.00
		flash_ctrl_csr_aliasing	1.131m	3.361ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	14.190s	18.248us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	14.110s	32.829us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	27.510s	22.553us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	1.675m	107.254us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	32.903m	150.573ms	3	3	100.00
		flash_ctrl_hw_rma_reset	25.570m	760.428ms	20	20	100.00
		flash_ctrl_lcmgr_intg	14.590s	15.931us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	54.900m	296.697ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	9.550m	20.987ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	4.984m	6.755ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.218h	50.872ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.573m	720.287us	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	33.760s	79.900us	40	40	100.00
		flash_ctrl_rw_evict_all_en	31.960s	80.062us	37	40	92.50
		flash_ctrl_re_evict	36.500s	417.299us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	9.026m	1.444ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	9.026m	1.444ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	19.562m	58.245ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	30.610s	827.162us	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	24.405m	567.568us	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	39.044m	6.304ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	15.826m	1.585ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	44.472m	890.411us	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	14.180s	15.616us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.439m	1.456ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.640s	42.554us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.840s	22.346us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	24.052m	619.025us	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.573m	13.433ms	50	50	100.00
		flash_ctrl_otp_reset	2.249m	147.119us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	32.903m	150.573ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	4.583m	8.382ms	39	40	97.50
		flash_ctrl_intr_wr	1.560m	5.363ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	9.150m	50.576ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	4.257m	132.341ms	9	10	90.00
V2	invalid_op	flash_ctrl_invalid_op	1.571m	1.015ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.244m	2.673ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	22.860s	62.952us	5	5	100.00
		flash_ctrl_ro_derr	2.859m	1.428ms	9	10	90.00
		flash_ctrl_rw_derr	13.538m	55.747ms	7	10	70.00
		flash_ctrl_derr_detect	1.061m	78.013us	0	5	0.00
		flash_ctrl_integrity	12.131m	4.112ms	4	5	80.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	22.990s	24.261us	5	5	100.00
		flash_ctrl_ro_serr	3.030m	6.069ms	10	10	100.00
		flash_ctrl_rw_serr	11.961m	6.970ms	7	10	70.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.444m	1.028ms	4	5	80.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.349m	741.514us	4	5	80.00
V2	scramble	flash_ctrl_wo	3.880m	5.222ms	18	20	90.00
		flash_ctrl_write_word_sweep	15.460s	80.779us	1	1	100.00
		flash_ctrl_read_word_sweep	14.270s	41.153us	1	1	100.00
		flash_ctrl_ro	2.314m	939.600us	20	20	100.00
		flash_ctrl_rw	10.810m	10.595ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	42.980s	360.998us	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	16.185m	163.844ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.253m	10.012ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.840s	178.941us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.480s	26.836us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	19.980s	109.487us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	19.980s	109.487us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	46.830s	25.214us	5	5	100.00
		flash_ctrl_csr_rw	17.870s	262.709us	20	20	100.00
		flash_ctrl_csr_aliasing	1.131m	3.361ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	34.750s	936.583us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	46.830s	25.214us	5	5	100.00
		flash_ctrl_csr_rw	17.870s	262.709us	20	20	100.00
		flash_ctrl_csr_aliasing	1.131m	3.361ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	34.750s	936.583us	20	20	100.00
V2		TOTAL			991	1013	97.83
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	15.910s	94.460us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	15.910s	94.460us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	15.910s	94.460us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	15.910s	94.460us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.170s	13.753us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.376h	3.990ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.309m	2.860ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.309m	2.860ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.309m	2.860ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	32.320s	67.100us	3	3	100.00
		flash_ctrl_wr_intg	15.020s	83.921us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.693m	70.296us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.249m	147.119us	80	80	100.00
		flash_ctrl_disable	22.640s	42.554us	50	50	100.00
		flash_ctrl_sec_info_access	1.647m	2.836ms	50	50	100.00
		flash_ctrl_connect	16.840s	22.346us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.390s	20.878us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.870s	262.709us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	15.910s	94.460us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.870s	262.709us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	15.910s	94.460us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.870s	262.709us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	15.910s	94.460us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.640s	42.554us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	32.320s	67.100us	3	3	100.00
		flash_ctrl_access_after_disable	14.700s	12.152us	3	3	100.00
V2S	sec_cm_mem_addr_infection	flash_ctrl_host_addr_infection	30.490s	43.973us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.640s	42.554us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	30.610s	827.162us	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	10.810m	10.595ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	11.961m	6.970ms	7	10	70.00
		flash_ctrl_rw_derr	13.538m	55.747ms	7	10	70.00
		flash_ctrl_integrity	12.131m	4.112ms	4	5	80.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	32.903m	150.573ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.376h	3.990ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.376h	3.990ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.376h	3.990ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.376h	3.990ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	25.040s	616.657us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.120s	18.406us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.400s	16.032us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.376h	3.990ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.376h	3.990ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.376h	3.990ms	5	5	100.00
V2S		TOTAL			147	147	100.00
V3	asymmetric_read_path	flash_ctrl_rd_ooo	44.250s	186.515us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1259	1281	98.28

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	44	80.00
V2S	13	13	13	100.00
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.14	95.68	93.92	98.31	91.84	98.17	96.89	98.15

Failure Buckets

Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 4 failures:
- Test flash_ctrl_serr_address has 1 failures.
  - 0.flash_ctrl_serr_address.103795986452727291817685286050452034199180742014323769889831185461737743538669
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_serr_address/latest/run.log
```
  Job ID: smart:a4925242-2a81-4fa2-8bad-bf4e6bb845cc
```
- Test flash_ctrl_wo has 2 failures.
  - 2.flash_ctrl_wo.14109787381370513169595258097038754081730443343290473025205286279470847891822
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_wo/latest/run.log
```
  Job ID: smart:b9eadb33-b5bb-4f54-bc29-533bddaf3216
```
  - 8.flash_ctrl_wo.24298426338351008582516626750290021440225842953600283257675515286601258306002
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_wo/latest/run.log
```
  Job ID: smart:acc60703-f934-4379-9d15-2eb046e7621e
```
- Test flash_ctrl_intr_wr_slow_flash has 1 failures.
  - 4.flash_ctrl_intr_wr_slow_flash.57150183924279215732769030730970676509591411889687954528523592419158616743193
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_intr_wr_slow_flash/latest/run.log
```
  Job ID: smart:1fa21faf-8e8f-4f13-a1e1-07e5e062b5ae
```

UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 4 failures:

Test flash_ctrl_serr_counter has 1 failures.

3.flash_ctrl_serr_counter.2134400545633658565221707461571166725537639277289996189750641943097895159314
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_serr_counter/latest/run.log

  UVM_ERROR @ 577896.8 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 577896.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_rw_serr has 3 failures.

5.flash_ctrl_rw_serr.58630815784822171027557093344623683983317713436378558221681449658116089950199
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 32660383.2 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 32660383.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.flash_ctrl_rw_serr.76502494807023621087541342550146539254495492957351924360441428431525368951743
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 13146440.7 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 13146440.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 4 failures:
- Test flash_ctrl_rw_evict_all_en has 3 failures.
  - 4.flash_ctrl_rw_evict_all_en.66187761766196057097971596833889784349148401177664113867616985586370052279721
    Line 289, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw_evict_all_en/latest/run.log
```
  UVM_ERROR @ 16996.3 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 16996.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 11.flash_ctrl_rw_evict_all_en.31540476194469577235791376971840841029580190777070097097760191423797517833970
    Line 292, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/11.flash_ctrl_rw_evict_all_en/latest/run.log
```
  UVM_ERROR @ 23463.3 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 23463.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test flash_ctrl_ro_derr has 1 failures.
  - 9.flash_ctrl_ro_derr.95055263780218544580260701447018776167464169213212889786139679519162012829829
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_ro_derr/latest/run.log
```
  UVM_ERROR @ 1080880.2 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 1080880.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:552) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 2 failures:

Test flash_ctrl_rw_derr has 2 failures.

2.flash_ctrl_rw_derr.19505988978407690083371993576460258348438617782913342486837270646763032906382
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rw_derr/latest/run.log

  UVM_ERROR @ 3214599.0 ns: (flash_ctrl_otf_scoreboard.sv:552) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (43119899598196747273356 [0x92188d1218a6210048c] vs 45481082839631569880204 [0x9a188d1218a6210048c])
  UVM_INFO @ 3214599.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.flash_ctrl_rw_derr.2262969582617108837233739003465740444296714549704655207764586603474892289964
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw_derr/latest/run.log

  UVM_ERROR @ 3617349.8 ns: (flash_ctrl_otf_scoreboard.sv:552) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (21442935707853211574656 [0x48a6c8300c002002180] vs 21442935707853211574664 [0x48a6c8300c002002188])
  UVM_INFO @ 3617349.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153701) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 0.flash_ctrl_derr_detect.8633616181260372156194635297698761741534676922386676495725031821287021324306
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 67270.3 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153701) { a_addr: 'h96894  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1b  a_opcode: 'h4  a_user: 'h2732a  d_param: 'h0  d_source: 'h1b  d_data: 'hfdac06b5  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd15  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 67270.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@231658) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 1.flash_ctrl_derr_detect.33165016029327644262147070940623547624045954949920938469576647069831844871255
    Line 303, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 79165.3 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@231658) { a_addr: 'hbc358  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h50  a_opcode: 'h4  a_user: 'h2612a  d_param: 'h0  d_source: 'h50  d_data: 'h60d6632e  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd0f  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 79165.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@232960) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 2.flash_ctrl_derr_detect.38556357726533515724367125302662250200125116280588293108900519661526770022192
    Line 303, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 78012.9 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@232960) { a_addr: 'h158e8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h75  a_opcode: 'h4  a_user: 'h271aa  d_param: 'h0  d_source: 'h75  d_data: 'h53f90c7  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd65  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 78012.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153151) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 3.flash_ctrl_derr_detect.86322652027908426479524654379526148665365633933790048978656699402842500010067
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 25264.3 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153151) { a_addr: 'ha0fdc  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h76  a_opcode: 'h4  a_user: 'h2782a  d_param: 'h0  d_source: 'h76  d_data: 'h7d546fc7  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd0b  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 25264.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154218) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 4.flash_ctrl_derr_detect.1511920779769918377942418255829771444523205032832398525593325917450738890887
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 56749.2 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154218) { a_addr: 'h53e3c  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h99  a_opcode: 'h4  a_user: 'h267aa  d_param: 'h0  d_source: 'h99  d_data: 'h4f8f4727  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd01  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 56749.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:552) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 1 failures:
- Test flash_ctrl_integrity has 1 failures.
  - 4.flash_ctrl_integrity.114400094923135238190261925141563319675998916438389856470253372120592568248228
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_integrity/latest/run.log
```
  UVM_ERROR @ 2153955.9 ns: (flash_ctrl_otf_scoreboard.sv:552) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (61963262438080987070976 [0xd1f09020c000a110200] vs 618902675230551969284 [0x218d00000908000e04])
  UVM_INFO @ 2153955.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:289) m_otf_scb [process_read] unexpected double bit error * has 1 failures:
- Test flash_ctrl_rw_derr has 1 failures.
  - 5.flash_ctrl_rw_derr.5172780675296355719313397718395177947347884455292539082996662736395600209631
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 1115077.4 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00003a90
  UVM_INFO @ 1115077.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *b2f1f63_16f09f18:ffffffff_16f09f* mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 37.flash_ctrl_intr_rd.3986262948993844792759844646644494488633767540775806076373468225665309436164
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/37.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 3453507.0 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    4: obs:exp    9b2f1f63_16f09f18:ffffffff_16f09f18  mismatch!!
  UVM_INFO @ 3453507.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```