FLASH_CTRL Simulation Results

Saturday July 20 2024 23:02:34 UTC

GitHub Revision: `e971cd9798`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 85433431889345478971181747401055702269263498582281270185582621732035232392187

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.779m	1.426ms	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	27.020s	195.112us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	45.830s	51.509us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	18.080s	47.355us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.163m	12.611ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.087m	1.594ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	20.360s	1.005ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	18.080s	47.355us	20	20	100.00
		flash_ctrl_csr_aliasing	1.087m	1.594ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.610s	15.555us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.880s	29.647us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.530s	28.727us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	1.530m	383.813us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	32.815m	337.811ms	3	3	100.00
		flash_ctrl_hw_rma_reset	18.094m	230.239ms	20	20	100.00
		flash_ctrl_lcmgr_intg	13.830s	26.654us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	42.896m	232.863ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	10.554m	19.058ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	3.252m	2.250ms	29	30	96.67
V2	full_memory_access	flash_ctrl_full_mem_access	59.465m	203.470ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.565m	1.158ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	32.650s	40.037us	37	40	92.50
		flash_ctrl_rw_evict_all_en	32.050s	43.804us	39	40	97.50
		flash_ctrl_re_evict	36.800s	168.174us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	9.398m	5.827ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	9.398m	5.827ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	12.142m	90.748ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	28.440s	1.685ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	21.876m	1.172ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	41.188m	62.725ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	17.931m	798.130us	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	50.069m	1.721ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	13.950s	15.674us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.912m	12.454ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.900s	54.847us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.840s	15.688us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	28.628m	9.675ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.335m	12.854ms	50	50	100.00
		flash_ctrl_otp_reset	2.263m	41.160us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	32.815m	337.811ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	5.337m	1.792ms	38	40	95.00
		flash_ctrl_intr_wr	1.490m	23.361ms	9	10	90.00
		flash_ctrl_intr_rd_slow_flash	7.952m	45.289ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	4.680m	320.992ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.530m	1.843ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.225m	645.319us	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	23.710s	19.240us	5	5	100.00
		flash_ctrl_ro_derr	3.086m	850.415us	10	10	100.00
		flash_ctrl_rw_derr	12.697m	77.426ms	8	10	80.00
		flash_ctrl_derr_detect	43.030s	45.366us	0	5	0.00
		flash_ctrl_integrity	11.228m	4.350ms	4	5	80.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	22.850s	85.228us	5	5	100.00
		flash_ctrl_ro_serr	2.760m	1.313ms	10	10	100.00
		flash_ctrl_rw_serr	13.144m	5.026ms	6	10	60.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.578m	4.841ms	4	5	80.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.823m	13.205ms	5	5	100.00
V2	scramble	flash_ctrl_wo	4.587m	12.839ms	18	20	90.00
		flash_ctrl_write_word_sweep	15.320s	39.580us	1	1	100.00
		flash_ctrl_read_word_sweep	14.240s	23.856us	1	1	100.00
		flash_ctrl_ro	2.252m	417.916us	20	20	100.00
		flash_ctrl_rw	11.604m	3.610ms	18	20	90.00
V2	filesystem_support	flash_ctrl_fs_sup	42.390s	1.247ms	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	18.591m	65.274ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.619m	10.012ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	15.150s	245.387us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.500s	32.912us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	19.850s	238.974us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	19.850s	238.974us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	45.830s	51.509us	5	5	100.00
		flash_ctrl_csr_rw	18.080s	47.355us	20	20	100.00
		flash_ctrl_csr_aliasing	1.087m	1.594ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.070s	301.316us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	45.830s	51.509us	5	5	100.00
		flash_ctrl_csr_rw	18.080s	47.355us	20	20	100.00
		flash_ctrl_csr_aliasing	1.087m	1.594ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.070s	301.316us	20	20	100.00
V2		TOTAL			988	1013	97.53
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	15.860s	41.754us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	15.860s	41.754us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	15.860s	41.754us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	15.860s	41.754us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.330s	14.788us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.335h	1.662ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.160m	2.653ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.160m	2.653ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.160m	2.653ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	31.860s	65.270us	3	3	100.00
		flash_ctrl_wr_intg	15.860s	214.852us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.779m	1.426ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.263m	41.160us	80	80	100.00
		flash_ctrl_disable	22.900s	54.847us	50	50	100.00
		flash_ctrl_sec_info_access	1.961m	36.512ms	50	50	100.00
		flash_ctrl_connect	16.840s	15.688us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.020s	38.844us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	18.080s	47.355us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	15.860s	41.754us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	18.080s	47.355us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	15.860s	41.754us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	18.080s	47.355us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	15.860s	41.754us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.900s	54.847us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	31.860s	65.270us	3	3	100.00
		flash_ctrl_access_after_disable	14.020s	23.126us	3	3	100.00
V2S	sec_cm_mem_addr_infection	flash_ctrl_host_addr_infection	30.250s	81.857us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.900s	54.847us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	28.440s	1.685ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	11.604m	3.610ms	18	20	90.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	13.144m	5.026ms	6	10	60.00
		flash_ctrl_rw_derr	12.697m	77.426ms	8	10	80.00
		flash_ctrl_integrity	11.228m	4.350ms	4	5	80.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	32.815m	337.811ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.335h	1.662ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.335h	1.662ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.335h	1.662ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.335h	1.662ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	25.050s	755.272us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.250s	15.653us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.460s	25.497us	4	5	80.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.335h	1.662ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.335h	1.662ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.335h	1.662ms	5	5	100.00
V2S		TOTAL			146	147	99.32
V3	asymmetric_read_path	flash_ctrl_rd_ooo	45.030s	440.828us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1255	1281	97.97

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	43	78.18
V2S	13	13	12	92.31
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.30	95.73	94.13	98.31	92.52	98.29	96.89	98.21

Failure Buckets

Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 7 failures:
- Test flash_ctrl_wo has 2 failures.
  - 7.flash_ctrl_wo.105486836516769039214083329319185736740679534798018862686040552988705950075632
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_wo/latest/run.log
```
  Job ID: smart:13a8d15b-7249-499a-a7d4-91e925e375d2
```
  - 17.flash_ctrl_wo.9408818725974865907472727912123305076554243088436434350646177083635115224542
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/17.flash_ctrl_wo/latest/run.log
```
  Job ID: smart:fcee3e0d-1f84-417d-be99-2a2632812374
```
- Test flash_ctrl_rw_derr has 1 failures.
  - 7.flash_ctrl_rw_derr.32752831076441080588806743526739680045143718407485583253090828625937425679460
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_rw_derr/latest/run.log
```
  Job ID: smart:e85bba27-3a84-47d9-bb31-f789768be5a6
```
- Test flash_ctrl_rw has 2 failures.
  - 8.flash_ctrl_rw.1874317630156474663854689672411510181939174858990418021380504784726068696130
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_rw/latest/run.log
```
  Job ID: smart:73ff32f5-a676-4812-a92e-ccdfea979b06
```
  - 10.flash_ctrl_rw.75156747408254786909154672418667358522346403444327689884516661165803349587953
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_rw/latest/run.log
```
  Job ID: smart:81497f48-b4cb-484e-8162-ccfbd67bf127
```
- Test flash_ctrl_intr_wr has 1 failures.
  - 8.flash_ctrl_intr_wr.111209597115116107601033675701960512596138351438231218043187970411355368255853
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_intr_wr/latest/run.log
```
  Job ID: smart:d96a9a1f-9e58-4973-a81c-db9078740136
```
- Test flash_ctrl_prog_reset has 1 failures.
  - 20.flash_ctrl_prog_reset.80373029094433342536304290821326251112177088576961456909446990563782073521196
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/20.flash_ctrl_prog_reset/latest/run.log
```
  Job ID: smart:a7acd4cc-b3f1-43d9-9386-9a82e099f0ba
```

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:552) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 3 failures:

Test flash_ctrl_rw_serr has 2 failures.

3.flash_ctrl_rw_serr.112803761227872350972765364289284102577543257942986377656317842161964175212294
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 7189461.9 ns: (flash_ctrl_otf_scoreboard.sv:552) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (23613244609559480258128 [0x5001399201000504e50] vs 23613172551965442330192 [0x5001299201000504e50])
  UVM_INFO @ 7189461.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.flash_ctrl_rw_serr.30982464666045209909528363106264639972276245277749453432610787995954280569759
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 2983211.1 ns: (flash_ctrl_otf_scoreboard.sv:552) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (23653338154213278751322 [0x502400202801c3c1a5a] vs 23653338154213010315866 [0x502400202800c3c1a5a])
  UVM_INFO @ 2983211.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_rw_derr has 1 failures.

8.flash_ctrl_rw_derr.94455048527359102986594619693923956542483353142284804361309832465975679337594
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_rw_derr/latest/run.log

  UVM_ERROR @ 11524009.2 ns: (flash_ctrl_otf_scoreboard.sv:552) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (4723465520127024357395 [0x1000f4090900900e013] vs 4723465520127024324627 [0x1000f40909009006013])
  UVM_INFO @ 11524009.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 2 failures:
- Test flash_ctrl_serr_counter has 1 failures.
  - 0.flash_ctrl_serr_counter.82391166002591167051094066762843923383497261739289825584728563704827304421275
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_serr_counter/latest/run.log
```
  UVM_ERROR @ 651172.5 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 651172.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_rw_serr has 1 failures.
  - 8.flash_ctrl_rw_serr.862954979838192649952121883643897644151735252028403657966505318181165462215
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_rw_serr/latest/run.log
```
  UVM_ERROR @ 112537.6 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 112537.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 2 failures:
- Test flash_ctrl_rw_evict_all_en has 1 failures.
  - 10.flash_ctrl_rw_evict_all_en.21765291806538412596974561370050594916886820126472279410740623966780166761186
    Line 292, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_rw_evict_all_en/latest/run.log
```
  UVM_ERROR @ 31916.9 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 31916.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_rw_evict has 1 failures.
  - 24.flash_ctrl_rw_evict.77163790300326404677971422220599649558056361705320286858337803059368042945020
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/24.flash_ctrl_rw_evict/latest/run.log
```
  UVM_ERROR @ 41034.8 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 41034.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_scoreboard.sv:481) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154539) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test flash_ctrl_derr_detect has 1 failures.

0.flash_ctrl_derr_detect.63625995756410462932790269432227233223916651625407976114010023195662048320221
Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_derr_detect/latest/run.log

  UVM_ERROR @ 77842.2 ns: (cip_base_scoreboard.sv:481) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154539) { a_addr: 'he0078  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2e  a_opcode: 'h4  a_user: 'h26eaa  d_param: 'h0  d_source: 'h2e  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h1  d_error: 'h1  d_sink: 'h0  d_user: 'heaa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 77842.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153239) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 1.flash_ctrl_derr_detect.48037764256411586972355194387397404620931884875692248551261680230230797897072
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 41523.0 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153239) { a_addr: 'hde250  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hc3  a_opcode: 'h4  a_user: 'h258aa  d_param: 'h0  d_source: 'hc3  d_data: 'h3702f9c7  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd53  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 41523.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153585) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 2.flash_ctrl_derr_detect.80809668219100637225536796633236862086352690175226914564858165913358800173751
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 130492.5 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153585) { a_addr: 'h666f8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h4  a_user: 'h2602a  d_param: 'h0  d_source: 'h0  d_data: 'hd8442e84  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd73  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 130492.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154645) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 3.flash_ctrl_derr_detect.68485039381261300477665033035926246949433479399551764542777615158560788640406
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 26686.2 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154645) { a_addr: 'he05c4  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h37  a_opcode: 'h4  a_user: 'h26e2a  d_param: 'h0  d_source: 'h37  d_data: 'hd4dfe457  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd1c  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 26686.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154682) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 4.flash_ctrl_derr_detect.112860851003237840740393878274020701356373188897988616977136552509422959364546
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 45365.8 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154682) { a_addr: 'h6daec  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hef  a_opcode: 'h4  a_user: 'h2792a  d_param: 'h0  d_source: 'hef  d_data: 'hcae9e48e  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd33  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 45365.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:289) m_otf_scb [process_read] unexpected double bit error * has 1 failures:
- Test flash_ctrl_integrity has 1 failures.
  - 4.flash_ctrl_integrity.65520183532397878896720304907260237582678706427250457355943655905803670647396
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_integrity/latest/run.log
```
  UVM_ERROR @ 10715944.8 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00004228
  UVM_INFO @ 10715944.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (*) != exp (*) has 1 failures:
- Test flash_ctrl_phy_ack_consistency has 1 failures.
  - 4.flash_ctrl_phy_ack_consistency.36969823806232762402536434058387540615592423106685748337989999530238257025540
    Line 284, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_phy_ack_consistency/latest/run.log
```
  UVM_ERROR @ 40987.1 ns: (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (0x2a) != exp (0x28)
  UVM_INFO @ 40987.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: * has 1 failures:
- Test flash_ctrl_rw_evict has 1 failures.
  - 5.flash_ctrl_rw_evict.40337729467442452889929739776739219412835472391288244160066387625806346821093
    Line 296, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_rw_evict/latest/run.log
```
  UVM_ERROR @ 12816.7 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: 0x0
  UVM_INFO @ 12816.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_scoreboard.sv:481) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@651175) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test flash_ctrl_rw_serr has 1 failures.

6.flash_ctrl_rw_serr.28291570820718409368059953768130482532012658040338077475536242059090474833704
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 317784.0 ns: (cip_base_scoreboard.sv:481) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@651175) { a_addr: 'h20038  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hc2  a_opcode: 'h4  a_user: 'h25e2a  d_param: 'h0  d_source: 'hc2  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h1  d_error: 'h1  d_sink: 'h0  d_user: 'heaa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 317784.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *ceb2cc0_4cba2ec4:ffffffff_4cba2ec* mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 13.flash_ctrl_intr_rd.7774361170938875950938529968451656131030545953128411786120417776197137952019
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 452981.4 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    0: obs:exp    4ceb2cc0_4cba2ec4:ffffffff_4cba2ec4  mismatch!!
  UVM_INFO @ 452981.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 1 failures:
- Test flash_ctrl_rw_evict has 1 failures.
  - 30.flash_ctrl_rw_evict.27858294895491648691404864107005977630797701823912875612432123420989821342320
    Line 303, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/30.flash_ctrl_rw_evict/latest/run.log
```
  UVM_FATAL @ 24051.0 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00001588
  UVM_INFO @ 24051.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *fa_adcf87bf:ffffffff_ffffffff mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 37.flash_ctrl_intr_rd.58112520122365417700690700786028065282735273487660360607573495440791938298269
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/37.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 3198796.2 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    4: obs:exp    272886fa_adcf87bf:ffffffff_ffffffff  mismatch!!
  UVM_INFO @ 3198796.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```