FLASH_CTRL Simulation Results

Sunday July 21 2024 23:02:06 UTC

GitHub Revision: `e971cd9798`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 60538554475599760039478308558126864941531727393021608909386829062452482962039

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.951m	9.620ms	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.940s	57.579us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	46.020s	92.346us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.580s	48.837us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.200m	6.769ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.181m	19.848ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	20.140s	723.526us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.580s	48.837us	20	20	100.00
		flash_ctrl_csr_aliasing	1.181m	19.848ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	14.170s	15.877us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.790s	217.403us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.950s	216.638us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	2.103m	274.058us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	52.386m	1.590s	3	3	100.00
		flash_ctrl_hw_rma_reset	16.801m	160.185ms	20	20	100.00
		flash_ctrl_lcmgr_intg	14.140s	15.704us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	49.686m	279.898ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	7.237m	4.177ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	4.220m	35.492ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.242h	232.813ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.275m	1.408ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	32.390s	101.148us	39	40	97.50
		flash_ctrl_rw_evict_all_en	32.110s	33.056us	38	40	95.00
		flash_ctrl_re_evict	36.910s	82.771us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	9.581m	5.786ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	9.581m	5.786ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	23.995m	107.002ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	31.040s	4.307ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	26.939m	6.710ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	39.441m	37.488ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	16.628m	710.984us	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	47.412m	4.328ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	13.880s	15.909us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.783m	5.414ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.840s	23.759us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.830s	13.522us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	30.585m	1.185ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	3.539m	14.579ms	50	50	100.00
		flash_ctrl_otp_reset	2.272m	225.473us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	52.386m	1.590s	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	5.214m	6.819ms	40	40	100.00
		flash_ctrl_intr_wr	1.250m	9.236ms	9	10	90.00
		flash_ctrl_intr_rd_slow_flash	6.211m	50.540ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	5.431m	104.846ms	9	10	90.00
V2	invalid_op	flash_ctrl_invalid_op	1.697m	16.229ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.208m	2.567ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	23.430s	34.663us	5	5	100.00
		flash_ctrl_ro_derr	3.252m	2.999ms	10	10	100.00
		flash_ctrl_rw_derr	11.704m	6.877ms	8	10	80.00
		flash_ctrl_derr_detect	1.020m	126.034us	0	5	0.00
		flash_ctrl_integrity	12.950m	16.125ms	4	5	80.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	23.060s	32.685us	5	5	100.00
		flash_ctrl_ro_serr	2.714m	658.506us	10	10	100.00
		flash_ctrl_rw_serr	13.365m	17.787ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.737m	12.562ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.753m	1.302ms	5	5	100.00
V2	scramble	flash_ctrl_wo	3.999m	16.775ms	20	20	100.00
		flash_ctrl_write_word_sweep	15.200s	83.153us	1	1	100.00
		flash_ctrl_read_word_sweep	14.560s	80.458us	1	1	100.00
		flash_ctrl_ro	2.469m	907.209us	20	20	100.00
		flash_ctrl_rw	11.746m	8.402ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	44.890s	737.360us	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	16.716m	101.005ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	4.186m	10.013ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.710s	254.439us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.370s	32.275us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	20.250s	123.985us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	20.250s	123.985us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	46.020s	92.346us	5	5	100.00
		flash_ctrl_csr_rw	17.580s	48.837us	20	20	100.00
		flash_ctrl_csr_aliasing	1.181m	19.848ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.810s	420.578us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	46.020s	92.346us	5	5	100.00
		flash_ctrl_csr_rw	17.580s	48.837us	20	20	100.00
		flash_ctrl_csr_aliasing	1.181m	19.848ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.810s	420.578us	20	20	100.00
V2		TOTAL			1000	1013	98.72
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.230s	12.508us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.230s	12.508us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.230s	12.508us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.230s	12.508us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.610s	15.008us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.332h	3.980ms	4	5	80.00
		flash_ctrl_tl_intg_err	15.202m	2.979ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.202m	2.979ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.202m	2.979ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	32.350s	117.286us	3	3	100.00
		flash_ctrl_wr_intg	15.940s	842.180us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.951m	9.620ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.272m	225.473us	80	80	100.00
		flash_ctrl_disable	22.840s	23.759us	50	50	100.00
		flash_ctrl_sec_info_access	1.533m	20.953ms	50	50	100.00
		flash_ctrl_connect	16.830s	13.522us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.210s	74.090us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.580s	48.837us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.230s	12.508us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.580s	48.837us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.230s	12.508us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.580s	48.837us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.230s	12.508us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.840s	23.759us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	32.350s	117.286us	3	3	100.00
		flash_ctrl_access_after_disable	14.520s	52.787us	3	3	100.00
V2S	sec_cm_mem_addr_infection	flash_ctrl_host_addr_infection	30.700s	67.099us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.840s	23.759us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	31.040s	4.307ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	11.746m	8.402ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	13.365m	17.787ms	10	10	100.00
		flash_ctrl_rw_derr	11.704m	6.877ms	8	10	80.00
		flash_ctrl_integrity	12.950m	16.125ms	4	5	80.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	52.386m	1.590s	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.332h	3.980ms	4	5	80.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.332h	3.980ms	4	5	80.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.332h	3.980ms	4	5	80.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.332h	3.980ms	4	5	80.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	24.390s	626.030us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.620s	43.725us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.410s	59.285us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.332h	3.980ms	4	5	80.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.332h	3.980ms	4	5	80.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.332h	3.980ms	4	5	80.00
V2S		TOTAL			146	147	99.32
V3	asymmetric_read_path	flash_ctrl_rd_ooo	45.240s	174.674us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1267	1281	98.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	48	87.27
V2S	13	13	12	92.31
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.15	95.68	93.97	98.31	91.84	98.19	96.89	98.18

Failure Buckets

Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 3 failures:
- Test flash_ctrl_intr_wr_slow_flash has 1 failures.
  - 0.flash_ctrl_intr_wr_slow_flash.94378309866407131971187588443934400420194321326561816379915118660989833276097
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_intr_wr_slow_flash/latest/run.log
```
  Job ID: smart:e092af35-7e4e-4a09-aed2-dbe49ff75c3b
```
- Test flash_ctrl_sec_cm has 1 failures.
  - 1.flash_ctrl_sec_cm.65367205944605764624184553466540291056650865549082196082579153399483275181951
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_sec_cm/latest/run.log
```
  Job ID: smart:a8056f56-66a5-4fac-aae5-855926cb944b
```
- Test flash_ctrl_intr_wr has 1 failures.
  - 4.flash_ctrl_intr_wr.61253546917026024342022545665526732367942024386136734558927174401581918326073
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_intr_wr/latest/run.log
```
  Job ID: smart:1562c31f-2889-49a9-80f8-71d6d5c0c861
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 3 failures:
- Test flash_ctrl_rw_evict_all_en has 2 failures.
  - 5.flash_ctrl_rw_evict_all_en.48549245383230888146260771308138762618398954771577780575434453670773899633454
    Line 299, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_rw_evict_all_en/latest/run.log
```
  UVM_ERROR @ 18955.2 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 18955.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 35.flash_ctrl_rw_evict_all_en.26947405527546595693799898151092759232687949912875689240035095395984717767316
    Line 294, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/35.flash_ctrl_rw_evict_all_en/latest/run.log
```
  UVM_ERROR @ 60898.9 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 60898.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_rw_evict has 1 failures.
  - 8.flash_ctrl_rw_evict.82717865209898357111040345228129243577149949320412935163436454326781949889508
    Line 291, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_rw_evict/latest/run.log
```
  UVM_ERROR @ 40114.2 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 40114.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:289) m_otf_scb [process_read] unexpected double bit error * has 2 failures:
- Test flash_ctrl_rw_derr has 2 failures.
  - 1.flash_ctrl_rw_derr.22155392512951175304346796052802512925170510068926915937990387107356475600603
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 1596870.3 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00004e00
  UVM_INFO @ 1596870.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.flash_ctrl_rw_derr.12058680272411557255354605765118701441984706853004568387271574160201024956805
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 5731696.6 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00004618
  UVM_INFO @ 5731696.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@152914) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 0.flash_ctrl_derr_detect.81086400369441352298792508969814618046166914168924585227325819740785209113612
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 27270.8 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@152914) { a_addr: 'hc25e4  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hce  a_opcode: 'h4  a_user: 'h252aa  d_param: 'h0  d_source: 'hce  d_data: 'hff1cdf1c  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd7e  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 27270.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:552) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 1 failures:
- Test flash_ctrl_integrity has 1 failures.
  - 0.flash_ctrl_integrity.93402309193516936015554946635709412953925204747567703794468213060423001021388
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_integrity/latest/run.log
```
  UVM_ERROR @ 16125412.5 ns: (flash_ctrl_otf_scoreboard.sv:552) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (21412283453717032216688 [0x488c32052040a082870] vs 20222333262904370660392 [0x44841400019150c0428])
  UVM_INFO @ 16125412.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153599) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 1.flash_ctrl_derr_detect.107528873674099919904948693798987166052606291869006683650007310674685353169005
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 41183.1 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153599) { a_addr: 'h1091c  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h89  a_opcode: 'h4  a_user: 'h2762a  d_param: 'h0  d_source: 'h89  d_data: 'he600b740  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd0e  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 41183.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153091) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 2.flash_ctrl_derr_detect.85722203721124533435637424117849230215843520617725424376949674492491730246482
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 78530.2 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153091) { a_addr: 'h1646c  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hbb  a_opcode: 'h4  a_user: 'h265aa  d_param: 'h0  d_source: 'hbb  d_data: 'hd3ce6eb0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd37  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 78530.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@155550) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 3.flash_ctrl_derr_detect.29035916569987883541802203246449423349041178927403255051504126767568801905706
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 25737.7 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@155550) { a_addr: 'h1e1ec  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hd2  a_opcode: 'h4  a_user: 'h2582a  d_param: 'h0  d_source: 'hd2  d_data: 'h8b174837  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd17  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 25737.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@227562) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 4.flash_ctrl_derr_detect.106990073094014329895659258110065716966011590470421123592584684854936674020414
    Line 303, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 126033.9 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@227562) { a_addr: 'hf3004  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hfb  a_opcode: 'h4  a_user: 'h2532a  d_param: 'h0  d_source: 'hfb  d_data: 'h4ef647d5  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd12  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 126033.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

FLASH_CTRL Simulation Results

Sunday July 21 2024 23:02:06 UTC

GitHub Revision: e971cd9798

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 60538554475599760039478308558126864941531727393021608909386829062452482962039

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `e971cd9798`